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| www.latticesemi.com 1 ds1027_07.0 orca ORT42G5 and ort82g5 0.6 to 3.7 gbps xaui and fc fpscs july 2008 data sheet ds1027 ?2008 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. introduction lattice semiconductor has developed a family of next generation fpscs intended for high-speed serial backplane data transmission. built on the series 4 recon?urable embedded system-on-a-chip (soc) architecture, the ORT42G5 and ort82g5 are made up of serdes transceivers containing four and eight channels respectively. each channel operates at up to 3.7 gbps across 26 inches of fr-4 backplane, with a full-duplex synchronous inter- face with built-in rx clock and data recovery (cdr), and transmitter preemphasis, along with more than 400k usable fpga system gates. the cdr circuitry available from lattice s high-speed i/o portfolio (syshsi ), has already been proven in numerous applications, to create interfaces for sonet/sdh, fibre channel, and ethernet (gbe, 10 gbe) applications. designers can also use these devices to drive high-speed data transfer across buses within any generic system. for example, designers can build a bridge for 10 g ethernet: the high-speed serdes interfaces can implement a xaui interface with a con?urable back-end interface such as xgmii. the ORT42G5 and ort82g5 can also be used to provide a full 10 g backplane data connection and, in the case of the ort82g5, provide both work and protection links between a line card and switch fabric. the ORT42G5 and ort82g5 provide a clockless high-speed interface for interdevice communication on a board or across a backplane. the built-in clock recovery of the ORT42G5 and ort82g5 allows for higher system perfor- mance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. network designers will bene? from the backplane transceiver as a network termination device. the device supports embed- ded 8b/10b encoding/decoding and link state machines for 10 g ethernet, and fibre channel. the ort82g5 is pinout compatible with a sister device, the orso82g5, which implements eight channels of serdes with sonet scrambling and cell processing. the ORT42G5 is pin compatible with the orso42g5, which implements four channels of serdes with sonet scrambling and cell processing. table 1. orca ORT42G5 and ort82g5 family ?available fpga logic device pfu rows pfu columns total pfus fpga max. user i/o luts ebr blocks 2 ebr bits 2 (k) fpga system gates (k) 1 ORT42G5 36 36 1296 204 10,368 12 111 333-643 ort82g5 36 36 1296 372 10,368 12 111 333-643 1. the embedded core, embedded system bus, fpga interface and mpi are not included in the above gate counts. the system gate ran ges are derived from the following: minimum system gates assumes 100% of the pfus are used for logic only (no pfu ram) with 40% ebr usage and two plls. maximum system gates assumes 80% of the pfus are for logic, 20% are used for pfu ram, with 80% ebr usage and four plls. 2. there are two 4k x 36 (144k bits each) ram blocks in the embedded core which are also accessible by the fpga logic.
lattice semiconductor orca ORT42G5 and ort82g5 data sheet 2 table of contents introduction .................................................................. 1 table of contents......................................................... 2 embedded function features...................................... 4 programmable features .............................................. 5 programmable logic system features........................ 6 description ................................................................... 7 what is an fpsc?........................................... 7 fpsc overview............................................... 7 fpsc gate counting ...................................... 7 fpga/embedded core interface .................... 7 fpsc design kit ............................................. 7 fpga logic overview..................................... 8 plc logic........................................................ 8 programmable i/o........................................... 8 routing............................................................ 9 system-level features ................................................ 9 microprocessor interface................................. 9 system bus ................................................... 10 phase-locked loops .................................... 10 embedded block ram .................................. 10 configuration................................................. 10 additional information ................................... 11 ORT42G5/ort82g5 overview ................................. 11 embedded core overview ............................ 11 serializer and deserializer (serdes) .......... 11 mux/demux block ...................................... 12 multi-channel alignment fifos..................... 12 xaui and fibre channel link state machines....................................................... 12 fpga/embedded core interface .................. 12 dual port rams ............................................ 13 fpsc configuration ...................................... 13 backplane transceiver core detailed description .... 13 8b/10b encoding and decoding .................... 14 transmit path (fpga to backplane) logic ... 16 8b/10b encoder and 1:10 multiplexer ........... 18 cml output buffer ........................................ 18 receive path (backplane to fpga) logic .... 19 link state machines...................................... 24 xaui link synchronization function............. 25 multi-channel alignment............................................. 27 ORT42G5 multi-channel alignment .............. 27 ort82g5 multi-channel alignment .............. 28 xaui lane alignment function (lane deskew) ....................................... 29 mixing half-rate, full-rate modes .................. 30 multi-channel alignment configuration ...................... 30 ORT42G5 configuration ............................... 30 ort82g5 configuration ............................... 31 ORT42G5 alignment sequence.................... 32 ort82g5 alignment sequence.................... 33 reference clocks and internal clock distribution...... 37 reference clock requirements .................... 37 synthesized and recovered clocks ............. 37 internal clock signals at the fpga/core interface for the ORT42G5 ................................................. 38 transmit and receive clock rates............... 39 transmit clock source selection .................. 39 recommended transmit clock distribution for the ORT42G5 .................................... 39 multi-channel alignment clocking strategies for the ORT42G5 ................... 41 internal clock signals at the fpga/core interface for the ort82g5 ................................................. 43 transmit and receive clock rates............... 44 transmit clock source selection .................. 44 recommended transmit clock distribution for the ort82g5 .................................... 45 multi-channel alignment clocking strategies for the ort82g5 ................... 47 reset operation ......................................................... 49 start up sequence for the ORT42G5 ........... 50 start up sequence for the ort82g5 ........... 51 test modes ................................................................ 52 loopback testing.......................................... 52 high-speed serial loopback at the cml buffer interface ....................................... 53 parallel loopback at the serdes boundary ................................................ 54 parallel loopback at mux/demux boundary, excluding serdes ............... 55 serdes characterization test mode (ort82g5 only)..................................... 55 embedded core block ram ...................................... 56 memory maps ............................................................ 59 definition of register types .......................... 59 ORT42G5 memory map................................ 59 ort82g5 memory map................................ 67 recommended board-level clocking for the ORT42G5 and ort82g5 ................. 73 absolute maximum ratings ....................................... 75 recommended operating conditions ........................ 75 serdes electrical and timing characteristics ......... 75 high speed data transmitter........................ 76 high speed data receiver............................ 77 external reference clock ............................. 79 embedded core timing characteristics ....... 79 pin descriptions ......................................................... 80 power supplies for ORT42G5 and ort82g5.......... 85 power supply descriptions ........................... 85 recommended power supply connections............................................ 85 recommended power supply filtering scheme................................................... 85 package information .................................................. 87 package pinouts ........................................... 87 lattice semiconductor orca ORT42G5 and ort82g5 data sheet 3 package thermal characteristics summary .............................................. 114 ja .............................................................. 114 jc .............................................................. 114 jc .............................................................. 115 jb .............................................................. 115 fpsc maximum junction temperature ...... 115 package thermal characteristics ............... 115 heat sink vendors for bga packages........ 115 package parasitics...................................... 116 package outline drawings.......................... 116 ordering information ................................................ 117 lattice semiconductor orca ORT42G5 and ort82g5 data sheet 4 embedded function features high-speed serdes with programmable serial data rates over the range 0.6 to 3.7 gbps. operation has been demonstrated on design tolerance devices at 3.7 gbps across 26 in. of fr-4 backplane and at 3.125 gbps across 40 in. of fr-4 backplane across temperature and voltage speci?ations. asynchronous operation per receive channel with the receiver frequency tolerance based on one reference clock per block channels (separate pll per channel). ability to select full-rate or half-rate operation per transmit or receive channel by setting the appropriate control registers. programmable one-half amplitude transmit mode for reduced power in chip-to-chip application. transmit preemphasis (programmable) for improved receive data eye opening. 32-bit (8b/10b) or 40-bit (raw data) parallel internal bus for data processing in fpga logic. provides a 10 gbps backplane interface to switch fabric. also supports multiple port cards at 2.5 gbps. 3.125 gbps serdes compliant with xaui serial data speci?ation for 10 g ethernet applications with protec- tion. ieee 802.3ae compliant xaui transceiver. includes embedded ieee 802.3ae-based xaui link state machine. compliant to fc-0 speci?ation for 1 gbps, 2gbps, 10 gbps (fc-xaui) modes. includes fibre channel link state machine. high-speed interface (hsi) function for clock/data recovery serial backplane data transfer without external clocks. serdes has low-power cml buffers. support for 1.5v/1.8v i/os. allows use with optical transceiver, coaxial copper media, shielded twisted pair wiring or high-speed backplanes such as fr-4. power down option of serdes hsi receiver or transmitter on a per-channel basis. automatic lock to reference clock in the absence of valid receive data. high-speed and low-speed loopback test modes. requires no external component for clock recovery and frequency synthesis. serdes characterization pins available to control/monitor the internal interface to one serdes block (ort82g5 only). serdes hsi automatically recovers from loss-of-clock once its reference clock returns to normal operating state. built-in boundary scan (ieee 1149.1 and 1149.2 jtag) for the programmable i/os, not including the serdes interface. fifos can align incoming data either across all eight channels (ort82g5 only), across one or two groups of four channels, or across two or four groups of two channels. alignment is done either using comma characters or by using the /a/ character in xaui mode. optionally, the alignment fifos can be bypassed for asynchronous operation between channels. (each channel includes its own clock and frame pulse or comma detect.) addition of two 4k x 36 dual-port rams with access to the programmable logic. the ort82g5 is pinout compatible to the orca orso82g5 sonet backplane driver fpsc. the ORT42G5 is pin compatible to the orso42g5. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 5 programmable features high-performance programmable logic: 0.16 ? 7-level metal technology. internal performance of >250 mhz. over 400k usable system gates. meets multiple i/o interface standards. 1.5v operation (30% less power than 1.8v operation) translates to greater performance. traditional i/o selections: lvttl (3.3v) and lvcmos (2.5v and 1.8v) i/os. per pin-selectable i/o clamping diodes provide 3.3v pci compliance. individually programmable drive capability: 24 ma sink/12 ma source, 12 ma sink/6 ma source, or 6 ma sink/3 ma source. two slew rates supported (fast and slew-limited). fast-capture input latch and input flip-flop (ff)/latch for reduced input setup time and zero hold time. fast open-drain drive capability. capability to register 3-state enable signal. off-chip clock drive capability. two-input function generator in output path. new programmable high-speed i/o: single-ended: gtl, gtl+, pecl, sstl3/2 (class i and ii), hstl (class i, iii, iv), zbt, and ddr. double-ended: lvds, bused-lvds, and lvpecl. programmable (on/off) internal parallel termination (100 ) is also supported for these i/os. ?ew capability to (de)multiplex i/o signals: new ddr on both input and output at rates up to 350 mhz (700 mhz effective rate). new 2x and 4x downlink and uplink capability per i/o (i.e., 50 mhz internal to 200 mhz i/o). enhanced twin-block programmable function unit (pfu): eight 16-bit look-up tables (luts) per pfu. nine user registers per pfu, one following each lut, and organized to allow two nibbles to act indepen- dently, plus one extra for arithmetic operations. new register control in each pfu has two independent programmable clocks, clock enables, local set/reset, and data selects. new lut structure allows ?xible combinations of lut4, lut5, new lut6, 4 1 mux, new 8 1 mux, and ripple mode arithmetic functions in the same pfu. 32 x 4 ram per pfu, con?urable as single- or dual-port. create large, fast ram/rom blocks (128 x 8 in only eight pfus) using the supplemental logic and interconnect cell (slic) decoders as bank drivers. soft-wired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu through fast internal routing which reduces routing congestion and improves speed. flexible fast access to pfu inputs from routing. fast-carry logic and routing to all four adjacent pfus for nibble-wide, byte-wide, or longer arithmetic func- tions, with the option to register the pfu carry-out. abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over previous architectures. hierarchical routing optimized for both local and global routing with dedicated routing resources. this results in faster routing times with predictable and ef?ient performance. slic provides eight 3-statable buffers, up to a 10-bit decoder, and pal -like and-or-invert (aoi) in each pro- grammable logic cell. new 200 mhz embedded block-port ram blocks, two read ports, two write ports, and two sets of byte lane enables. each embedded ram block can be con?ured as: lattice semiconductor orca ORT42G5 and ort82g5 data sheet 6 1?12 x 18 (block-port, two read/two write) with optional built in arbitration. 1?56 x 36 (dual-port, one read/one write). 1?k x 9 (dual-port, one read/one write). 2?12 x 9 (dual-port, one read/one write for each). 2 rams with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). supports joining of ram blocks. two 16 x 8-bit content addressable memory (cam) support. fifo 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9. constant multiply (8 x 16 or 16 x 8). dual variable multiply (8 x 8). embedded 32-bit internal system bus plus 4-bit parity interconnects fpga logic, microprocessor interface (mpi), embedded ram blocks, and embedded standard cell blocks with 100 mhz bus performance. included are built- in system registers that act as the control and status center for the device. built-in testability: full boundary scan (ieee 1149.1 and draft 1149.2 jtag). programming and readback through boundary scan port compliant to ieee draft 1532:d1.7. ts_all testability function to 3-state all i/o pins. new temperature-sensing diode. improved built-in clock management with programmable phase-locked loops (pplls) provide optimum clock modi?ation and conditioning for phase, frequency, and duty cycle from 20 mhz up to 420 mhz. multiplication of the input frequency up to 64x and division of the input frequency down to 1/64x possible. new cycle stealing capability allows a typical 15% to 40% internal speed improvement after ?al place and route. this feature also enables compliance with many setup/hold and clock to out i/o speci?ations and may provide reduced ground bounce for output buses by allowing ?xible delays of switching output buffers. per channel pseudo-random bit sequence (prbs) generator and checker in fpga logic. programmable logic system features pci local bus compliant for fpga i/os. improved powerpc ? 860 and powerpc ii high-speed synchronous microprocessor interface can be used for con?uration, readback, device control, and device status, as well as for a general-purpose interface to the fpga logic, rams, and embedded standard cell blocks. glueless interface to synchronous powerpc processors with user-con?urable address space provided. new embedded system bus facilitates communication among the microprocessor interface, con?uration logic, embedded block ram, fpga logic, and embedded standard cell blocks. variable size bused readback of con?uration data capability with the built-in microprocessor interface and sys- tem bus. internal, 3-state, and bidirectional buses with simple control provided by the slic. new clock routing structures for global and local clocking signi?antly increases speed and reduces skew (<200 ps for or4e04). new local clock routing structures allow creation of localized clock trees. two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved setup/hold and clock to out performance. new double-data rate (ddr) and zero-bus turn-around (zbt) memory interfaces support the latest high- speed memory interfaces. new 2x/4x uplink and downlink i/o capabilities interface high-speed external i/os to reduced speed internal logic. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 7 description what is an fpsc? fpscs, or ?ld-programmable system chips, are devices that combine ?ld-programmable logic with asic or mask-programmed logic on a single device. fpscs provide the time to market and the ?xibility of fpgas, the design effort savings of using soft intellectual property (ip) cores, and the speed, design density, and economy of asics. fpsc overview lattice s series 4 fpscs are created from series 4 orca fpgas. to create a series 4 fpsc, several columns of programmable logic cells (see fpga logic overview section for fpga logic details) are added to an embedded logic core. other than replacing some fpga gates with asic gates, at greater than 10:1 ef?iency, none of the fpga functionality is changed?ll of the series 4 fpga capability is retained including: the embedded block rams, microprocessor interface (mpi), boundary scan, etc. the columns of programmable logic are replaced at the right of the device, allowing pins from the replaced columns to be used as i/o pins for the embedded core. the remainder of the device pins retain their fpga functionality. fpsc gate counting the total gate count for an fpsc is the sum of its embedded core (standard-cell/asic gates) and its fpga gates. because fpga gates are generally expressed as a usable range with a nominal value, the total fpsc gate count is sometimes expressed in the same manner. standard-cell asic gates are, however, 10 to 25 times more silicon- area ef?ient than fpga gates. therefore, an fpsc with an embedded function is gate equivalent to an fpga with a much larger gate count. fpga/embedded core interface the interface between the fpga logic and the embedded core has been enhanced to allow for a greater number of interface signals than on previous fpsc architectures. compared to bringing embedded core signals off-chip, this on-chip interface is much faster and requires less power. all of the delays for the interface are precharacterized and accounted for in the lattice isplever system software. series 4 based fpscs expand this interface by providing a link between the embedded block and the multi-master 32-bit system bus in the fpga logic. this system bus allows the core easy access to many of the fpga logic func- tions including the embedded block rams and the microprocessor interface. clock spines also can pass across the fpga/embedded core boundary. this allows for fast, low-skew clocking between the fpga and the embedded core. many of the special signals from the fpga, such as done and global set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the fpga as a system. for even greater system ?xibility, fpga con?uration rams are available for use by the embedded core. this allows for user-programmable options in the embedded core, in turn allowing for greater ?xibility. multiple embed- ded core con?urations may be designed into a single device with user-programmable control over which con?u- rations are implemented, as well as the capability to change core functionality simply by recon?uring the device. fpsc design kit development is facilitated by an fpsc design kit which, together with isplever system software and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an fpsc implementation. included in the kit are the fpsc con?uration manager, complied verilog simulation models, hspice and/or ibis models for i/o buffers, and complete online documentation. the kit's software coupled with the design environment, provides a seamless fpsc design environment. more information can be obtained by vis- iting the lattice web site at www .latticesemi.com or contacting a local sales of?e. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 8 fpga logic overview the orca series 4 architecture is a new generation of sram-based programmable devices from lattice. it includes enhancements and innovations geared toward today s high-speed systems on a single chip. designed with networking applications in mind, the series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. orca series 4 devices contain many new patented enhance- ments and are offered in a variety of packages and speed grades. the hierarchical architecture of the logic, clocks, routing, ram, and system-level blocks create a seamless merge of fpga and asic designs. modular hardware and software technologies enable system-on-chip integration with true plug-and-play design implementation. the architecture consists of four basic elements: programmable logic cells (plcs), programmable i/o cells (pios), embedded block rams (ebrs), plus supporting system-level features. these elements are interconnected with a rich routing fabric of both global and local wires. an array of plcs is surrounded by common interface blocks which provide an abundant interface to the adjacent plcs or system blocks. routing congestion around these crit- ical blocks is eliminated by the use of the same routing fabric implemented within the programmable logic core. each plc contains a pfu, slic, local routing resources, and con?uration ram. most of the fpga logic is per- formed in the pfu, but decoders, pal-like functions, and 3-state buffering can be performed in the slic. the pios provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, uplink and downlink functions, and other functions on two output signals. large blocks of 512 x 18 block-port ram complement the existing distributed pfu memory. the ram blocks can be used to implement ram, rom, fifo, multiplier, and cam. some of the other system-level functions include the mpi, plls, and the embedded system bus (esb). plc logic each pfu within a plc contains eight 4-input (16-bit) luts, eight latches/ffs, and one additional flip-flop that may be used independently or with arithmetic functions. the pfu is organized in a twin-block fashion; two sets of four luts and ffs that can be controlled independently. each pfu has two independent programmable clocks, clock enables, local set/reset, and data selects. luts may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. the carry-out of either mode may be registered in the ninth ff for pipelining. each pfu may also be con?ured as a synchronous 32 x 4 single- or dual-port ram or rom. the ffs (or latches) may obtain input from lut outputs or directly from invertible pfu inputs, or they can be tied high or tied low. the ffs also have programmable clock polarity, clock enables, and local set/reset. the slic is connected from plc routing resources and from the outputs of the pfu. it contains eight 3-state, bidi- rectional buffers, and logic to perform up to a 10-bit and function for decoding, or an and-or with optional invert to perform pal-like functions. the 3-state drivers in the slic and their direct connections from the pfu outputs make fast, true, 3-state buses possible within the fpga, reducing required routing and allowing for real- world system performance. programmable i/o the series 4 pio addresses the demand for the ?xibility to select i/os that meet system interface requirements. i/os can be programmed in the same manner as in previous orca devices, with the additional new features which allow the user the ?xibility to select new i/o types that support high-speed interfaces. each pio contains four programmable i/o pads and is interfaced through a common interface block to the fpga array. the pio is split into two pairs of i/o pads with each pair having independent clock enables, local set/reset, and global set/reset. on the input side, each pio contains a programmable latch/flip-flop which enables very fast latching of data from any pad. the combination provides for very low setup requirements and zero hold times for lattice semiconductor orca ORT42G5 and ort82g5 data sheet 9 signals coming on-chip. it may also be used to demultiplex an input signal, such as a multiplexed address/data sig- nal, and register the signals without explicitly building a demultiplexer with a pfu. on the output side of each pio, an output from the plc array can be routed to each output flip-flop, and logic can be associated with each i/o pad. the output logic associated with each pad allows for multiplexing of output signals and other functions of two output signals. the output ff, in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. the output buffer signal can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. in addition, this 3- state signal can be registered or nonregistered. the series 4 i/o logic has been enhanced to include modes for speed uplink and downlink capabilities. these modes are supported through shift register logic, which divides down incoming data rates or multiplies up outgoing data rates. this new logic block also supports high-speed ddr mode requirements where data is clocked into and out of the i/o buffers on both edges of the clock. the new programmable i/o cell allows designers to select i/os which meet many new communication standards permitting the device to hook up directly without any external interface translation. they support traditional fpga standards as well as high-speed, single-ended, and differential-pair signaling. based on a programmable, bank-ori- ented i/o ring architecture, designs can be implemented using 3.3v, 2.5v, 1.8v, and 1.5v referenced output levels. routing the abundant routing resources of the series 4 architecture are organized to route signals individually or as buses with related control signals. both local and global signals utilize high-speed buffered and nonbuffered routes. one plc segmented (x1), six plc segmented (x6), and bused half chip (xhl) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance. eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be sourced from dedicated i/o pads, plls, or the plc logic. secondary and edge-clock routing is available for fast regional clock or control signal routing for both internal regions and on device edges. secondary clock routing can be sourced from any i/o pin, plls, or the plc logic. the improved routing resources offer great ?xibility in moving signals to and from the logic core. this ?xibility translates into an improved capability to route designs at the required speeds when the i/o signals have been locked to speci? pins. system-level features the series 4 also provides system-level functionality by means of its microprocessor interface, embedded system bus, block-port embedded block rams, universal programmable phase-locked loops, and the addition of highly tuned networking speci? phase-locked loops. these functional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in today s high-speed networking systems. microprocessor interface the mpi provides a glueless interface between the fpga and powerpc microprocessors. programmable in 8-, 16, and 32-bit interfaces with optional parity to the motorola powerpc 860 bus, it can be used for con?uration and readback, as well as for fpga control and monitoring of fpga status. all mpi transactions utilize the series 4 embedded system bus at 66 mhz performance. a system-level microprocessor interface to the fpga user-de?ed logic following con?uration, through the system bus, including access to the embedded block ram and general user-logic, is provided by the mpi. the mpi sup- ports burst data read and write transfers, allowing short, uneven transmission of data through the interface by including data fifos. transfer accesses can be single beat (1 x 4 bytes or less), 4-beat (4 x 4 bytes), 8-beat (8 x 2 bytes), or 16-beat (16 x 1 bytes). lattice semiconductor orca ORT42G5 and ort82g5 data sheet 10 system bus an on-chip, multimaster, 8-bit system bus with 1-bit parity facilitates communication among the mpi, con?uration logic, fpga control, status registers, embedded block rams, as well as user logic. utilizing the amba speci?a- tion rev 2.0 ahb protocol, the embedded system bus offers arbiter, decoder, master, and slave elements. master and slave elements are also available for the user-logic and a slave interface is used for control and status of the embedded backplane transceiver portion of the device. the system bus control registers can provide control to the fpga such as signaling for reprogramming, reset func- tions, and pll programming. status registers monitor init, done, and system bus errors. an interrupt controller is integrated to provide up to eight possible interrupt resources. bus clock generation can be sourced from the micro- processor interface clock, con?uration clock (for slave con?uration modes), internal oscillator, user clock from routing, or from the port clock (for jtag con?uration modes). phase-locked loops up to eight plls are provided on each series 4 device, with four user plls generally provided for fpscs. pro- grammable plls can be used to manipulate the frequency, phase, and duty cycle of a clock signal. each ppll is capable of manipulating and conditioning clocks from 20 mhz to 200 mhz. frequencies can be adjusted from 1/8x to 8x, the input clock frequency. each programmable pll provides two outputs that have different multiplication fac- tors but can have the same phase relationships. duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. an automatic input buffer delay compensation mode is available for phase delay. each ppll provides two outputs that can have programmable (12.5% steps) phase differences. embedded block ram new 512 x 18 block-port ram blocks are embedded in the fpga core to signi?antly increase the amount of mem- ory and complement the distributed pfu memories. the ebrs include two write ports, two read ports, and two byte lane enables which provide four-port operation. optional arbitration between the two write ports is available, as well as direct connection to the high-speed system bus. additional logic has been incorporated to allow signi?ant ?xibility for fifo, constant multiply, and two-variable multiply functions. the user can con?ure fifo blocks with ?xible depths of 512k, 256k, and 1k including asyn- chronous and synchronous modes and programmable status and error ?gs. multiplier capabilities allow a multiple of an 8-bit number with a 16-bit ?ed coef?ient or vice versa (24-bit output), or a multiple of two 8-bit numbers (16- bit output). on-the-? coef?ient modi?ations are available through the second read/write port. two 16 x 8-bit cams per embedded block can be implemented in single match, multiple match, and clear modes. the ebrs can also be preloaded at device con?uration time. con?uration the fpgas functionality is determined by internal con?uration ram. the fpgas internal initialization/con?ura- tion circuitry loads the con?uration data at power up or under system control. the con?uration data can reside externally in an eeprom or any other storage media. serial eeproms provide a simple, low pin-count method for con?uring fpgas. the ram is loaded by using one of several con?uration modes. supporting the traditional master/slave serial, master/slave parallel, and asynchronous peripheral modes, the series 4 also utilizes its microprocessor interface and embedded system bus to perform both programming and readback. daisy chaining of multiple devices and partial recon?uration are also permitted. other con?uration options include the initialization of the embedded-block ram memories and fpsc memory as well as system bus options and bit stream error checking. programming and readback through the jtag (ieee 1149.2) port is also available meeting in-system programming (isp ) standards (ieee 1532 draft). lattice semiconductor orca ORT42G5 and ort82g5 data sheet 11 additional information contact your local lattice representative for additional information regarding the orca series 4 fpga devices, or visit the lattice web site at www .latticesemi.com . ORT42G5/ort82g5 overview the ORT42G5 and ort82g5 fpscs provide high-speed backplane transceivers combined with fpga logic. they are based on the 1.5v or4e04 orca fpga and have 36 x 36 arrays of programmable logic cells (plcs). the embedded core, which contains the backplane transceivers is attached to the right side of the device and is inte- grated directly into the fpga array. a top level diagram of the basic chip con?uration is shown in figure 1. embedded core overview the embedded core portions of the ORT42G5 and ort82g5 contain respectively four or eight clock and data recovery (cdr) macrocells and serialize/deserialize (serdes) blocks and support 8b/10b ( ieee 802.3.2002) encoded serial links. it is intended for high-speed serial backplane data transmission. figure 1 shows the ORT42G5 and ort82g5 top level block diagram and the basic data ?w. boundary scan for the ORT42G5/ort82g5 only includes programmable i/os and does not include any of the embedded block i/os. figure 1. ORT42G5/ort82g5 top level block diagram the serial channels can each operate at up to 3.7 gbps (2.96 gbps data rate) with a full-duplex synchronous inter- face with built-in clock recovery (cdr). the 8b/10b encoding provides guaranteed ones density for the cdr, byte alignment, and error detection. the core is also capable of frame synchronization and physical link monitoring and contains independent 4k x 36 ram blocks. overviews of the various blocks in the embedded core are presented in the following paragraphs. serializer and deserializer (serdes) the serdes portion of the core contains two transceiver blocks for serial data transmission at a selectable data rate of 0.6 to 3.7 gbps. each serdes channel features high-speed 8b/10b parallel i/o interfaces to other core blocks and high-speed cml interfaces to the serial links. the serdes circuitry consists of receiver, transmitter, and auxiliary functional blocks. the receiver accepts high- speed (up to 3.7 gbps) serial data. based on data transitions, the receiver locks an analog receive pll for each channel to retime the data, then demultiplexes the data down to parallel bytes and an accompanying clock. the transmitter operates in the reverse direction. parallel bytes are multiplexed up to 3.7 gbps serial data for off- chip communication. the transmitter generates the necessary 3.7 ghz clocks for operation from a lower speed ref- erence clock. serdes w/ clock/data byte- wide data 8b/10b decoder/encoder 4 or 8 full- 0.6 gbps data duplex serial channels to 3.7 gbps 0.6 gbps data to 3.7 gbps cml i/os orca series 4 fpga logic standard fpga i/os recovery 4:1 mux/1:4 demux and multi-channel alignment fifos lattice semiconductor orca ORT42G5 and ort82g5 data sheet 12 the transceivers are controlled and con?ured through the system bus in the fpga logic and through the external 8-bit microprocessor interface of the fpga. each channel has associated dedicated registers that are readable and writable. there are also global registers for control of common circuitry and functions. the serdes performs 8b/10b encoding and decoding for each channel. the 8b/10b transmission code can sup- port either ethernet or fibre channel speci?ations for serial encoding/decoding, special characters, and error detection. the user can disable the 8b/10b decoder to receive raw 10-bit words which will be rate reduced by the serdes. if this mode is chosen, the user must bypass the multi-channel alignment fifos. the serdes block contains its own dedicated plls for both transmit and receive clock generation. the user pro- vides a reference clock of the appropriate frequency. the receiver plls extract the clock from the serial input data and retime the data with the recovered clock. mux/demux block the mux/demux block converts the data format for the high speed serial links to a wide, low-speed format for crossing the core/fpga interface. the intermediate interface to the serdes macrocell runs at 1/10th the bit rate of the data lane. the mux/demux converts the data rate and bus width so the interface to the fpga core can run at 1/4th this intermediate frequency, giving a range of 25.0-92.5 mhz for the data rates into and out of the fpga logic. multi-channel alignment fifos in the ort82g5, the eight incoming data channels (four per serdes block) can be independent of each other or can be synchronized in several ways. two channels within a serdes block can be aligned together; channels a and b and/or channels c and d. alternatively, four channels in a serdes block can be aligned together to form a communication channel with a bandwidth of 10 gbps. finally, the alignment can be extended across both serdes blocks to align all eight channels. individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. in the ORT42G5, the four incoming data channels (two per serdes block) can be independent of each other or can be synchronized in two ways. two channels, channels c and d, within either serdes block can be aligned together. alternatively, all four channels can be aligned together to form a communication channel with a bandwidth of 10 gbps. individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. xaui and fibre channel link state machines two separate link state machines are included in the architecture. a xaui link state machine is included in the embedded core modeled after the ieee 802.3ae standard. a separate state machine for fibre channel is also implemented. fpga/embedded core interface in 8b/10b mode, the fpga logic will receive/transmit 32-bits of data (up to 92.5 mhz) and 4 k_ctrl bits from/to the embedded core. there are 8 data streams in each direction plus additional timing, status and control signals. data sent to the fpga can be aligned using comma (/k/) characters or /a/ character as speci?d either by fibre channel or by ieee 802.3ae for xaui based interfaces. the alignment character is made available to the fpga along with the data. the special characters k28.1, k28.5 and k28.7 are treated as valid comma characters by the serdes. if the receive channel alignment fifos are bypassed, then each channel will provide its own receive clock in addi- tion to data and comma character detect signals. if the 8b/10b decoders are bypassed, then 40-bit data streams are passed to the fpga logic. no channel alignment can be done in 8b/10b bypass mode. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 13 dual port rams in addition to the backplane interface blocks, there are two independent memory blocks in the asb. each memory block has a capacity of 4k words by 36 bits. it has one read port, one write port, and four byte-write-enable (active- low) signals. the read data from the memory block is registered so that it works as a pipelined synchronous mem- ory block. fpsc con?uration con?uration of the ORT42G5 and ort82g5 occurs in two stages: fpga bitstream con?uration and embedded core setup. prior to becoming operational, the fpga goes through a sequence of states, including power up, initialization, con- ?uration, start-up, and operation. the fpga logic is con?ured by standard fpga bit stream con?uration means as discussed in the series 4 fpga data sheet. after the fpga con?uration is complete, the options for the embedded core are set based on the contents of reg- isters that are accessed through the fpga system bus. the system bus itself can be driven by an external powerpc compliant microprocessor via the mpi block or via a user master interface in fpga logic. a simple ip block that drives the system by using the user register interface and very little fpga logic is available in the mpi/system bus technical note. this ip block sets up the embedded core via a state machine and allows the ORT42G5 and ort82g5 to work in an independent system without an external microprocessor interface. backplane transceiver core detailed description the following sections describe the various logic blocks in the embedded core portion of the fpsc. the fpga section of the fpsc is identical to an orca or4e04 fpga except that the pads on one edge of the fpga chip are replaced by the embedded core. for a detailed description of the programmable logic functions, please see the orca series 4 fpga data sheet and related application and technical notes. the major functional blocks in the embedded core include: two serializer-deserializer (serdes) blocks and clock and data recovery (cdr) circuitry 8b/10b encoder/decoders transmit pre-emphasis circuitry 4-to-1 multiplexers (mux) and 1-to-4 demultiplexers (demux) fibre channel synchronization state machine xaui link alignment state machine alignment fifos embedded 4k x 36 ram blocks (independent from transceiver logic). a top level block diagram of the embedded core logic is shown in figure 2. the embedded ram blocks are not shown. the external pins for the embedded core are listed later in this data sheet in table 41 and the signals at the transceiver embedded core/fpga interface for the ORT42G5 are listed in table 8, table 9 and table 11; and for the ort82g5, in table 8, table 10 and table 12. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 14 figure 2. top level block diagram, embedded core logic (channel ac) the embedded core provides transceiver functionality for four or eight serial data channels and is organized into two blocks, each supporting two or four channels. each channel is identi?d by both a block identi?r [a:b] and a channel identi?r [a:d]. in the ORT42G5 only the channel identi?rs c and d are used. (this naming convention follows that of the ort82g5). the data channels can operate independently or they can be combined together (aligned) to achieve higher bit rates. the mode operation of the core is de?ed by a set of control registers, which can be written through the sys- tem bus interface. also, the status of the core is stored in a set of status registers, which can be read through the system bus interface. the transmitter section for each channel accepts 40 bits of data or 32 bits of data and eight control/status bits from the fpga logic and optionally encodes the data using 8b/10b encoding. it also accepts the low-speed reference clock at the refclk input and uses this clock to synthesize the internal high-speed serial bit clock. the data is then serialized and the serialized data are available at the differential cml output terminated in 86 to drive either an optical transmitter or coaxial media or circuit board/backplane. the receiver section receives high-speed serial data at its differential cml input port. these data are fed to the clock recovery section which generates a recovered clock and retimes the data. the retimed data are also deseri- alized and optionally 8b/10b decoded. the receiver also optionally recognizes the comma characters or code viola- tions and aligns the bit stream to the proper word boundary. the resulting parallel data is optionally passed to the multi-channel alignment block before it is presented to the fpga logic. 8b/10b encoding and decoding in 8b/10b mode, the fpga logic will receive/transmit 32 bits of data and 4 k_ctrl bits from/to the embedded core. in the transmit direction, four additional input bits force a negative disparity present state. the embedded core logic will encode the data to or decode the data from a 10-bit format according to the fc-ph ansi x3.230:1994 standard (which is also the encoding used by the ieee 802.3ae ethernet standard). this encoding/decoding scheme also allows for the transmission of special characters and supports error detection. common logic, block a next channel . . . last channel (bd) backplane serial links receive channel ac 2:1 mux (x40) demux block link state machine rx ser- des block multi - channel alignment block tx serdes block interface and mux block transmit channel ac rck78a tck78a mrwdac[39:0] cv_selac rwckac rsys_clk_a2 tsys_clk_ac twdac[31:0] tcommac[3:0] . . . fpga logic hdout[p:n]_ac 2 2 hdin[p:n]_ac refclk[p:n]_a 2 lattice semiconductor orca ORT42G5 and ort82g5 data sheet 15 following the de?itions and conventions used in de?ing the 8b/10b coding rules, each valid coded character has a name corresponding to its 8-bit binary value: dxx.y for data characters kxx.y for special characters xx = the 5-bit input value, base 10, for bits abcde y = the 3-bit input value, base 10, for bits fgh an 8b/10b encoder is designed to maintain a neutral average disparity. disparity is the difference between the number of 1s and 0s in the encoded word. neutral disparity indicates the number of 1s and 0s are equal. positive disparity indicates more 1s than 0s. negative disparity indicates more 0s than 1s. the average disparity deter- mines the dc component of the signals on the serial line. running disparity is a record of the cumulative disparity of every encoded word, and is tracked by the encoder. in order to maintain neutral disparity, two different codings are de?ed for each data value. the 8b/10b encoder in the transmit path selects between (+) and (-) encoded word based on calculated disparity of the present data to maintain neutral disparity in the receive path, the clock and data recovery blocks retime the incoming data and 8b/10b decoders generate 8- bit data based on the received 10-bit data. a sequence of valid 8b/10b coded characters has a maximum run length of 5 bits (i.e., 5 consecutive ones or 5 consecutive zeros before a mandatory bit transition). this assures adequate transitions for robust clock recovery. the recovered data is aligned on a 10-bit boundaries by detecting and aligning to special characters in the incom- ing data stream. data is word aligned using the comma (/k/) character. a comma character is a special character that contains a unique pattern (0011111 or its complement 1100000) in the 10-bit space that makes it useful for delimiting word boundaries. the special characters k28.1, k28.5 and k28.7 contain this comma sequence and are treated as valid comma characters by the serdes. the following table shows all of the valid special characters. all of the special characters are made available to the fpga logic; however only the comma characters are used by the serdes logic. the different codings that are possible for each data value are shown as encoded word (+) and encoded word (-). the table also illustrates the 8b/10b bit labeling convention. the bit positions of the 8-bit characters are labeled as h,g,f,e,d,c,b and a and the bit positions of the 10-bit encoded characters are labeled as a, b, c, d, e, i, f, g, h, and j. the encoded words are transmitted serially with bit ? transmitted ?st and bit ? transmitted last. table 2. valid special characters k character hgf edcba 765 43210 k control encoded word (? encoded word (+) abcdei fghj abcdei fghj k28.0 000 11100 1 001111 0100 110000 1011 k28.1 /comma/ 001 11100 1 001111 1001 110000 0110 k28.2 010 11100 1 001111 0101 110000 1010 k28.3 /a/ 011 11100 1 001111 0011 110000 1100 k28.4 100 11100 1 001111 0010 110000 1101 k28.5 /comma/ 101 11100 1 001111 1010 110000 0101 k28.6 110 11100 1 001111 0110 110000 1001 k28.7 /comma/ 111 11100 1 001111 1000 110000 0111 k23.7 111 10111 1 111010 1000 000101 0111 k27.7 111 11011 1 110110 1000 001001 0111 k29.7 111 11101 1 101110 1000 010001 0111 k30.7 111 11110 1 011110 1000 100001 0111 lattice semiconductor orca ORT42G5 and ort82g5 data sheet 16 transmit path (fpga to backplane) logic the transmitter section accepts four groups of either 8-bit unencoded data or 10-bit encoded data at the parallel interface to the fpga logic. it also uses the reference clock, refclk[p:n]_[a:b] to synthesize an internal high- speed serial bit clock. the serialized transmitted data are available at the differential cml output pins to drive either an optical transmitters, coaxial media or a circuit board backplane. as shown in figure 3, the basic blocks in the transmit path include: embedded core/fpga interface and 4:1 multiplexer low speed parallel core/fpga interface 4:1 multiplexer transmit serdes 8b/10b encoder 10:1 multiplexer cml output buffer detailed descriptions of the logic blocks are given in following sections. detailed descriptions of transmit clock dis- tribution, including the transmit pll are given in later sections of this data sheet. figure 3. basic logic blocks, transmit path, single channel (typical reference clock frequency) 4 fifo 4:1 mux (x9) pll cml buffer with pre- emphasis 10:1 mux 8b/10b encoder (with bypass) interface and mux block tx serdes block stbd_xx[7:0] stbd_xx[8] stbd_xx[9] stbc311_xx 8 8-bit data k-control force-ve disparity 312.5 mhz hdoutp_xx hdoutn_xx refclkp_[a:b] refclkn_[a:b] cml buffer backplane serial link fpga logic twdxx[31:0] 32 tcommaxx[3:0] 4 tbit9xx[3:0] 4 tsys_clk_xx mux tck78[a:b] 78.125 mhz tcksel[0:1][a:b] logic common to block from other channel or channels to other channel or channels from control register { { for ORT42G5: xx = [ac, ad, bc or bd] for ort82g5: xx = [aa, ab, ... bd] 156.25 mhz lattice semiconductor orca ORT42G5 and ort82g5 data sheet 17 embedded core/fpga logic interface and 4:1 multiplexer these blocks provide the data formatting and transmit data and clock signal transfers between the embedded core and the fpga logic. control and status registers in the fpga portion of the chip contain to control the transmit logic and record status. these bits are passed to the core using the fpga system bus and are described in later sections of this data sheet. the low-speed transmit interface consists of a clock and 4 data bytes, each with an accompanying control bit. the data bytes are conveyed to the mux via the twdxx[31:0] ports (where xx represents the channel label [aa,...,bd] or [ac, ad, bc, bd]). the control bits are tcommax[3:0] which de?e whether the input byte is to be interpreted as data or as a special character and tbit9xx[3:0] which are used to force a negative disparity present state. the data and control signals are synchronized to the transmit clock, tsys_clk_xx. both the data and control are strobed into the core on the rising edge of tsys_clk_xx. note that each tbit9xx[3:0] controls the disparity of the encoded version of its corresponding data byte. setting bit tbit9ac[3] to 1, for instance, will force the 8b/10b encoder to assess a current negative running disparity state. this will cause it to encode twdac[31:24] positively (more 1 s than 0 s). setting tbit9xx to 0 will leave the encoder free to alternate between positive and negative encoding to maintain a zero running disparity. the mux is responsible for taking 40 bits of data/control at the low-speed transmit interface and up-converting it to 10 bits of data/control at the serdes transmit interface. the mux has 2 clock domains - one based on the clock received from the serdes block and a second that comes from the fpga at 1/4 the frequency of the serdes clock. the time sequence of interleaving data/control values is shown in figure 4. figure 4. transmit mux block timing - single channel serdes block the serdes block accepts either 8-bit data to be encoded or 10-bit unencoded data at the parallel input port from the mux/demux block. it also accepts the reference clock at the refclk_[a:b] input and uses this clock to syn- thesize the internal high-speed serial bit clock. the internal stbc311xx clock is derived from the reference clock. the frequency of this clock depends on the set- ting of the half-rate/full-rate control bit setting the mode of the serdes and the frequency of the refclk_[a:b] and/or that of the high-speed serial data. a falling edge on the stbc311xx clock port will cause a new data charac- ter to be transferred into the serdes block. the latency from the serdes block input to the high-speed serial output is 5 stbc311xx clock cycles, as shown in figure 5. pqrs t xyz stbdxx[9:0] latency = 4 tsys_clk_xx clocks twdxx[31:24], tsys_clk_xx s 8 r 8 z 8 y 8 10-bit wide data twdxx[23:16], twdxx[15:8], r 7-0, y 7-0, tcommaxx[3] tcommaxx[2] tcommaxx[1] tcommaxx[0] twdxx[7:0], s 7-0, z 7-0, tbit9xx[0] tbit9xx[1] tbit9xx[2] tbit9xx[3] q 9 r 9 s 9 z 9 y 9 x 9 p 7-0, p 8 t 7-0, q 8 t 8 x 8 q 7-0, x 7-0, p 9 t 9 lattice semiconductor orca ORT42G5 and ort82g5 data sheet 18 figure 5. transmit path timing - single serdes channel each block also sends a clock to the fpga logic. this clock, tck78[a,b], is sourced from one of the four mux blocks and has the same frequency as tsys_clk_xx, but arbitrary phase. within each mux block, the low fre- quency clock output is obtained by dividing by 4 the serdes stbc311x clock which is used internally to synchro- nize the transmit data words. tcksel control bits select the channel to source tck78[a:b]. the internal signals stbdxx[9:0] (where xx is represents aa...bd or ac, ad, bc, bd) from the mux block carry unencoded character data and control bits. the 10th bit (stbdxx[9]) of each data lane into the serdes is used to force a negative disparity present state. 8b/10b encoder and 1:10 multiplexer the 8b/10b encoder encodes the incoming 8-bit data into a 10-bit format as described previously. the input signals to the block, stbdxx[7:0] are used for the 8-bit unencoded data. stbdxx[8] is used as the k_control input to indi- cate whether the 8 data bits need to be encoded as special characters (k_control = 1) or as data characters (k_control = 0). when stbdxx[9:0] = 1, a negative disparity present state is forced. when the encoder is bypassed stbdxx[9:0] serve as the data bits for the 10-bit unencoded data. within the de?ition of the 8b/10b transmission code, the bit positions of the 10-bit encoded transmission charac- ters are labeled as a, b, c, d, e, i, f, g, h, and j in that order. bit a corresponds to stbdxx[0], bit b to stbdxx[1], bit c to stbdxx[2], bit d to stbdxx[3], bit e to stbdxx[4], bit i to stbdxx[5], bit f to stbdxx[6], bit g to stbdxx[7], bit h to stbdxx[8], and bit j to stbdxx[9]. the 10-bit wide parallel data is converted to serial data by the 10:1 multiplexer. the serial data are then sent to the cml output buffer and are transmitted serially with stbdxx[0] transmitted ?st and stbdxx[9] transmitted last. cml output buffer the transmitter s cml output buffer is terminated on-chip in 86 ohms to optimize the data eye as well as to reduce the number of discrete components required. the differential output swing reaches a maximum of 1.2 v pp in the normal amplitude mode. a half amplitude mode can be selected via con?uration register bit hamp_xx. half ampli- tude mode can be used to reduce power dissipation when the transmission medium has minimal attenuation or for testing of the integrity (loss) of the physical medium. a programmable preemphasis circuit is provided to boost the high frequencies in the transmit data signal to maxi- mize the data eye opening at the far-end receiver. preemphasis is particularly useful when the data are transmitted over backplanes or low-quality coax cables which have a frequency-dependent amplitude loss. for example, for fr4 material at 2.5 ghz, the attenuation compared to the 1.0 ghz value is about 3 db. the attenuation is a result of skin effect loss of the pcb conductor and the dielectric loss of the pcb substrate. this attenuation causes inter- symbol interface which results in the closing of the data eye opening at the receiver. ..... pqrs t xyz stbdxx[9:0] ..... stbc311xx ..... hdout_xx p 4 p 5 p 6 p 7 p 8 p 9 p 0 p 1 p 2 p 3 latency = 5 stbc311x clocks lattice semiconductor orca ORT42G5 and ort82g5 data sheet 19 since this effect is predictable for a given type of pcb material, it is possible to compensate for this effect in two ways - transmitter preemphasis and receiver equalization. each of these techniques boosts the high frequency components of the signal but transmit preemphasis is preferred due to the ease of implementation and the better power utilization. it also gives a better signal-to-noise ratio because receiver equalization ampli?s both the signal and the noise at the receiver applying too much preemphasis when it is not required, for example when driving a short backplane path, will also degrade the data eye opening at the receiver. in the ORT42G5 and ort82g5 the degree of transmit preemphasis can be programmed with a two-bit control from the microprocessor interface as shown in table 3. the high-pass transfer function of the preemphasis circuit is given by the following equation, where the value of a is shown in table 3. h(z) = (1 ?az ? ) (1) table 3. preemphasis settings receive path (backplane to fpga) logic the receiver section receives high-speed serial data at the external differential cml input pins. these data are fed to the clock recovery section which generates a recovered clock and retimes the data. therefore the receive clocks are asynchronous between channels. the retimed data are deserialized and presented as an 8-bit decoded or a 10-bit unencoded parallel data on the output port. the receiver also optionally recognizes comma characters, detects code violations and aligns the bit stream to the proper word boundary. as shown in figure 6, the basic blocks in the receive path include: receive serdes block cml input buffer receive pll 1:10 demultiplexer (demux) clock and data recovery (cdr) section 10b/8b decoder 1:4 demultiplexer and embedded core/fpga interface 1:4 demux low speed parallel embedded core/fpga logic interface multi-channel alignment logic pe1 pe0 amount of preemphasis (a) 0 0 0% (no preemphasis) 0 1 12.5% 1 0 12.5% 1 1 25% lattice semiconductor orca ORT42G5 and ort82g5 data sheet 20 figure 6. basic logic blocks, receive path, single channel (typical reference clock frequency) each channel provides its own received clock, received data and k-character detect signals to the fpga logic. incoming data from multiple channels can be aligned using comma (/k/) characters or /a/ character (as speci?d either in fibre channel speci?ations or in ieee 802.3ae for xaui based interfaces). if the 8b/10b decoders are bypassed, then 40-bit data streams are passed to the fpga logic. no channel alignment can be done in this 8b/10b bypass mode. detailed descriptions of data synchronization, of the serdes, demux and multi-channel alignment blocks and of the fibre channel and xaui state machines are given in following sections. receive clock distribution is described in a later section of this data sheet. synchronization the serdes rx logic performs four levels of synchronization on the incoming serial data stream. each level builds upon the previous, providing ?st bit, then byte (character), then channel (32-bit word), and ?ally multi-chan- nel alignment. each step is described functionally in the following paragraphs. the details of the logical implemen- tations are described in subsequent sections. bit alignment is the task of the clock/data recovery (cdr) block. this block utilizes a pll that locks to the transi- tions in the incoming high-speed serial data stream, and outputs the extracted clock as well as the data. if the pll is unable to lock to the serial data stream, it instead locks to refclk[a:b] to stabilize the voltage-controlled oscil- lator (vco), and periodically switches back to the serial data stream to again attempt synchronization. this pro- cess continues until a valid input data stream is detected and lock is achieved. the cdr can maintain lock on data as long as the input data stream contains an adequate data ?ye (i.e., jitter is within speci?ation) and the maxi- mum data stream run length is not exceeded. refclkp_[a:b] refclkn_[a:b] refclk buffer mux rck78[a:b] 78.125 mhz rcksel[0:1][a:b] logic common to block from other channel or channels to other channel or channels from control register { { pll cml buffer 1:10 demux 8b/10b encoder (with bypass) hdinp_xx hdin_xx cdr byte align rx serdes block xaui state machine 1:4 demux (x 10) 156.25 mhz fifo multi- channel alignment fpga logic backplane serial link rwckxx 78.125 mhz multi-channel alignment block 78.125 mhz 78.125 mhz clock ralignxx[3:0] align character detect 4 4 rwbit8xx[3:0] 4 bits k-control 32 rwdxx[31:0] 32-bit data rsys_clk_x# 78.125 mhz 2:1 mux (x40) mrwdxx[39:0] cv_selxx 4 rwbit9xx[3:0] 40 36 32-bit data 4 bits k-ctrl synchronization status bits see table 8 fibre channel state machine srbd_xx[0:9] demux block scvxx 312.5 mhz clocks 10 2 sbytsync_xx swdsync_xx for ORT42G5: xx = [ac, ad, bc, bd] x# = [a2, b2] for ort82g5: xx = [aa, ab, ... bd] x# = [a1, ...b2] 3 fpga logic lattice semiconductor orca ORT42G5 and ort82g5 data sheet 21 bit alignment times fall into two categories: realignment when the input serial data stream experiences an abrupt phase change (as may occur when protection switching is performed between two paths having different delays), and alignment from a no-signal condition. realignment is very quick, since the pll s vco is already locked on fre- quency and only needs to adapt to the new phase. this re-alignment has been observed to require no more than one microsecond when refclk[a:b] = 156.25 mhz. alignment from a no-signal condition has two components. first, there is the re-acquisition to the data s frequency and phase. the time required for re-acquisition to the data s frequency is minimized by logic that periodically switches the pll to lock to the refclk[a:b] when it fails to lock on the serial data stream, thus limiting the vco s frequency wander. second, there is the time spent while the pll is locking to refclk[a:b], which can be from zero to a maximum value, depending on when the serial data stream becomes valid in relation to the pll s switch- ing to/from refclk[a:b]. this alignment has been observed to require no more than 4 microseconds when ref- clk = 156.25 mhz. byte alignment occurs once valid bit alignment is achieved. the byte aligner looks for a particular 7-bit sequence (either 0011111 or its complement, 1100000) that, in data that has been 8b/10b encoded per fibre channel or ieee 802.3ae speci?ations, only occurs in the comma (/k/) characters k28.1, k28.5 and k28.7. byte alignment only occurs when the enbysync_xx signal for that channel is active high, and re-alignment occurs on each 7-bit sequence encountered. however, if enbysync_xx is asserted active high and no comma character is encoun- tered, and then is brought inactive low, the channel will still perform one byte alignment operation on the next comma character. byte alignment occurs immediately when an alignment sequence is detected, so the lock time is only one clock period. note: each time the byte aligner performs an alignment, it also corrects the phase of the internal rbc_xx clock. this can result in the ?tretching of the clock by a half-phase in order to cause the output data to align with the ris- ing edge of rbc_xx. word (32-bit) alignment can occur after the fibre channel (xaui_mode_xx = 0) or xaui (xaui_mode_xx = 1) state machine has reached the in-synchronization state. in fibre channel mode, synchronization (wdsync_xx = 1) will occur after three ordered sets of data have been received in the absence of any code violations. after this, the next ordered set will cause the output data to be aligned such that the comma character is in the most signi? cant byte. thus, 32-bit word alignment has been achieved when four ordered sets have been detected. the time required is directly dependent on comma-character density. note: once word alignment is accomplished, no further alignment occurs unless and until wdsync_xx goes to zero and back to one again. comma characters that are not located in the most signi?ant byte position will not trigger further re-alignment while wdsync_xx is active. this behavior is as de?ed by the fibre channel speci? cation. however, it means that, if the channel experiences an abrupt delay change (as could occur if an external mux performs a protection switch between two links) and if the delay change is close enough to a full character or characters that not enough code violations are generated to cause loss of wdsync_xx, the channel could become misaligned and remain that way inde?itely. as mentioned above, this behavior is that de?ed by the fibre channel speci?ation. in xaui mode, as the state diagram later in this data sheet indicates, three error-free code-groups containing com- mas must be detected before synchronization is declared. multi 2, 4 or 8 (ort82g5 only) channel alignment (lane alignment in xaui mode) can be performed after 32- bit word alignment is complete. multi-channel alignment is described in later sections of this data sheet. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 22 receive cml input buffer and serdes the receiver section receives high-speed serial data at its differential cml input port. the receive input is an ac- coupled input. the received data is sent to the clock recovery section which generates a recovered clock and retimes the data. valid data will be received after the receive pll has locked to the input data frequency and phase. the received serial data is converted to10-bit wide parallel data by the 1:10 demultiplexor. clock recovery is per- formed by the serdes block for each of the eight receive channels. this recovered data is then aligned to a 10-bit word boundary by detecting and aligning to a comma special character. word alignment is done for either polarity of the comma character. the 10-bit code word is passed to the 8b/10b decoder, which provides an 8-bit byte of data, a special character indicator bit and a sbytsync_xx signal (where again xx is a placeholder for aa,...,bd or ac, ad, bc, bd). data from a serdes channel is sent to the demux block in 10-bit raw form or 8-bit decoded form across the srbd_xx [9:0] port with a latency of approximately 14-23 cycles (bit periods of the incoming data). accompanying this data are the comma-character indicator (sbytsync_xx), link-state indicator (swdsync_xx), clocks (srbc0_xx, and srbc1_xx), and code-violation indicator (scvxx). the two internal clocks operated at twice the reference clock frequency. figure 7 shows the receive path timing for a single serdes channel. figure 7. receive path timing for a single serdes channel with the 8b10br_xx control bit of the serdes channel set to 1, the data presented at srbd_xx[9:0] will be decoded characters. bit 8 will indicate whether srbdxx[7:0] represents an ordinary data character (bit 8 = 0), or whether srbd_xx[7:0] represents a special character, like a comma. bit 9 may be either a code violation indicator or one of seven out of synchronization state indicators, as described later. when 8b10br is set to 0, the data at srbd_xx[9:0] will not be decoded. the xaui link-state machine should not be used in this mode of operation. when in xaui mode, the mux/demux looks for /a/ (as de?ed in ieee 802.3ae v.2.1) characters for channel alignment and requires the characters to be in decoded form for this to work 1:4 demultiplexer (demux) the1:4 demux has to accumulate four sets of characters presented to it at the serdes receive interface and put these out at one time at the low-speed receive interface. another task of the 1:4 demux is to recognize the synchronizing event and adjust the 4-byte boundary so that the synchronizing character leads off a new 4-byte word. in fibre channel mode, this synchronizing character is a comma. this feature will be referred to as demux word alignment in other areas of this document. demux word embedded core ..... ..... pq r s t xyz srbd_xx[9:0] ..... ..... srbc0_xx srbc1_xx ..... sbytsync_xx, svcxx q 0 r 8 r 9 s 0 p 4 p 5 p 6 p 7 p 8 p 9 ..... p 0 p 1 p 2 p 3 r 2 r 3 r 4 r 5 r 6 r 7 s 1 s 2 s 3 s 4 p hdin[p:n]_xx srbd_xx[9:0] 1-bit 10-bit ..... ..... latency = approx 23 cycles lattice semiconductor orca ORT42G5 and ort82g5 data sheet 23 alignment will only occur when the communication channel is synchronized. when there is no synchronization of the link, the 1:4 demux will continue to output 4-byte words at some arbitrary, but constant, boundary. there are 2 control register bits available for each channel for word alignment. they are dowdalgn_xx and nowdalgn_xx. the dowdalgn_xx bit is positive edge triggered. writing a 0 followed by a 1 to this register bit will cause the corresponding demux to look for a new comma character and align the 32-bit word such that the comma is in the most signi?ant byte position. it is important that the comma is in the most signi?ant byte position since the multi-channel aligner looks for comma in the most signi?ant byte only. typically, it is not necessary to set the dowdalgn_xx bit. when the link state machine loses synchronization (demuxwas_xx register bit is 0), the demux block automatically looks for a new comma character irrespective of whether the dowdalgn_xx bit is set or not. however, as discussed earlier, the comma character may become misaligned without the fibre channel link state machine indicating a loss of synchronization. in such cases, the dowdalgn_xx bit must be toggled to force resynchronization. the nowdalgn_xx bit is a level-sensitive bit. if it is a 1, then the demux does not dynamically alter the word boundary based on comma and swdsync_xx output of the serdes. this might be useful if a channel were con- ?ured to bypass the multi-channel alignment fifo and raw 40-bits of data are directed from serdes to fpga. in fibre channel mode, the default setting (nowdalgn_xx = 0) causes the word boundary to be set as soon as the serdes swdsync_xx output is a 1 and a comma character has been detected. the character that is the comma becomes the most-signi?ant portion of the demultiplexed word. when the serdes loses link synchroni- zation it will drop swdsync_xx low. the demux will begin search for word alignment as soon as swdsync_xx goes to 1 again. the demux passes on to the channel alignment fifo block a set of control signals that indicate the location of the synchronizing event. ralign_xx[3:0] are these indicators. if there is no link synchronization, all of the ralign_xx[[3:0] bits will be zeros independent of synchronizing events that come in. when the link is synchro- nized, then the bit that corresponds to the time of the synchronization event will be set to a 1. the relationship between a time sequence of values input at srbdxx[7:0] to the values output at rwd_xx[39:0] is shown in figure 8. a parallel relationship exists between srbdx[8] and rwbit8_xx[3:0] as well as between srbd_xx[9] and rwbit9_xx[3:0]. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 24 figure 8. receive demux block for a single serdes channel one clock per block of two or four channels, called rck78[a,b], is sent to the fpga. the control bits rcksel[a,b] are used to select the channel that is the source for these clocks. link state machines two link state machines are included in the device, one for xaui applications and a second for fibre channel appli- cations. the fibre channel link state machine is responsible for establishing a valid link between the transmitter and the receiver and for maintaining link synchronization. the machine is initially in the loss of synchronization (los) state upon power-on reset. this is indicated by wdsync_xx = 0. while in this state, the machine looks for a partic- ular number of consecutive idle ordered sets without any invalid data transmission in between before declaring syn- chronization achieved. achievement of synchronization is indicated by asserting wdsync_xx = 1. speci?ally, the machine looks for three continuous idle ordered sets without any misaligned comma character or any running dis- parity based code violation in between. in the event of any such code violation, the machine would reset itself to the ground state and start its search for the idle ordered sets again. a typical valid sequence for achieving link synchro- nization would be k28.5 d21.4 d21.5 d21.5 repeated three times. in the synchronization achieved state, the machine constantly monitors the received data and looks for any kind of code violation that might result due to running disparity errors. if it were to receive four such consecutive invalid words, the link machine loses its synchronization and once again enters the loss of synchronization state (los). a pair of valid words received by the machine overcomes the effect of a previously encountered code violation. los is indicated by the status of wdsync_xx output which now transitions from 1 to 0. at this point the machine attempts to establish the link yet again. figure 9 shows the state diagram for the fibre channel link state machine. los is also indicated by demuxwas_xx status register bit. this bit is set to 0 during loss of synchronization. pq r s t xyz srbdxx[9:0] 10-bit p 7-0 40-bit rwd_xx[31:24] rwd_xx[23:16] rwd_xx[15:8] rwd_xx[7:0] latency = 4 rsys_clk [a1,...,b2] clocks p 8 p 9 t 7-0 t 8 t 9 q 7-0 q 8 q 9 x 7-0 x 8 x 9 r 7-0 r 8 r 9 y 7-0 y 8 y 9 s 7-0 s 8 s 9 z 7-0 z 8 z 9 rwbit8_xx[3] rwbit9_xx[3] rwbit8_xx[2] rwbit8_xx[1] rwbit8_xx[0] rwbit9_xx[2] rwbit9_xx[1] rwbit9_xx[0] lattice semiconductor orca ORT42G5 and ort82g5 data sheet 25 figure 9. fibre channel link state machine state diagram xaui link synchronization function for each lane, the receive section of the xaui link state machine incorporates a synchronization state machine that monitors the status of the 10-bit alignment. a 10-bit alignment is done in the serdes based on a comma charac- ter such as k28.5. a comma (0011111 or its complement 1100000) is a unique pattern in the 10-bit space that can- not appear across the boundary between any two valid 10-bit code-groups. this property makes the comma useful for delimiting code-groups in a serial stream.this mechanism incorporates a hysteresis to prevent false synchroni- zation and loss of synchronization due to infrequent bit errors. for each lane, the sync_complete signal is disabled until the lane achieves synchronization. the synchronization state diagram is shown in figure 10. this state machine is modeled after draft ieee 802.3ae, version 2.1 but will also operate with version 4.1 implementations. table 4 and table 5 describe the state variables used in figure 10. the xaui state machine does not have any control over the serdes byte aligner. it is the user s responsibility to control the byte aligner through software access of register map addresses 30800 and 30900. note that it takes four idle ordered sets (e.g. k28.5, dxx.y, dxx.y, dxx.y) to bring the state machine from a loss_of_sync to a synch_acq d_1 state. when back-to-back commas are used instead, it takes a total of ?e com- mas to achieve the same result as with idle ordered sets. table 4. xaui link synchronization state diagram ?functions function description sync_complete indication that alignment code-group alignment has been established at the boundary indicated by the most recently received comma. cg_comma indication that a valid code-group, with correct running disparity, containing a comma has been received. cg_good indication that a valid code-group with the correct running disparity has been received. cg_bad indication that an invalid code-group has been received. no_comma indication that comma timer has expired. the timer is initialized upon receipt of a comma. los = 1 last ordered set received: vw rst link synchronization achieved (wdsync = 1) os cv os os os cv cv cv cv cv 1vw 1vw 1vw 2 vw 2 vw 2 vw a b c d e h g f loss of synchronization (wdsync_xx = 0) lsm_enable + powerup_reset vw: valid word (a 4 character based word having no code violation) with at least cv: code violation (running disparity based on illegal comma position) os: idle ordered set (a 4 character based word having comma as the 1st character) 1vw: first valid word after a code violation two preceeding valid words 2vw: second valid word after a code violation lattice semiconductor orca ORT42G5 and ort82g5 data sheet 26 figure 10. xaui link synchronization state diagram table 5. xaui link synchronization state diagram notation ?variables variable description sync_status fail: lane is not synchronized (correct 10-bit alignment has not been established). ok: lane is synchronized. ok_noc: lane is synchronized but a comma character has not been detected in the past 200 code groups. enable_cdet true: align subsequent 10-bit words to the boundary indicated by the next received comma. false: maintain current 10-bit alignment. gd_cg current number of consecutive cg_good indications. loss_of_sync sync_status <= fail enable_cdet <= true sync_complete reset comma_detect_1 enable_cdet <= false cg_bad cg_bad cg_comma cg_comma cg_bad comma_detect_2 comma_detect_3 cg_comma sync_acq d_1 sync_acq d_1a sync_status <= ok no_comma & cg_bad sync_status <= ok_noc cg_bad cg_comma sync_ acq d_2 sync_ acq d_3 sync_ acq d_4 sync_ acq d_2a sync_ acq d_3a sync_ acq d_4a gd_cg <= gd_cg + 1 gd_cg <= 0 cg_good cg_good x (gd_cg ! = 3) cg_bad cg_good x (gd_cg = 3) cg_good x (gd_cg ! = 3) cg_bad cg_good*(gd_cg=3) cg_good cg_bad cg_good x (gd_cg = 3) cg_good cg_good x (gd_cg ! = 3) cg_bad cg_bad cg_bad gd_cg <= 0 gd_cg <= 0 gd_cg <= gd_cg + 1 gd_cg <= gd_cg + 1 ~ no_comma & cg_bad lattice semiconductor orca ORT42G5 and ort82g5 data sheet 27 multi-channel alignment the alignment fifo allows the transfer of all data to the system clock. the multi-channel alignment block (figure 6) allows the system to be con?ured to allow the frame alignment of multiple slightly varying data streams. this optional alignment ensures that matching serdes streams will arrive at the fpga end in perfect data syn- chronization. each channel is provided with a 24 word x 36-bit fifo. the fifo can perform two tasks: (1) to change the clock domain from receive clock to a clock from the fpga side, and (2) to align the receive data over 2, 4, or 8 channels. this fifo allows a timing budget of ?30.4 ns that can be allocated to skew between the data lanes and for trans- fer to the system clock. the input to the fifo consists of 36 bits of demultiplexed data, ralign_xx[3:0], rwd_xx[31:0], and rwbit8_xx[3:0]. the four ralign_xx bits are control signals, and can be the alignment character detect signals indicating the pres- ence of a comma character in fibre channel mode and the /a/ character in xaui mode. the other 32 rwd_xx bits are the 8-bit data bytes from the 8b/10b decoder. the alignment character, if present, is the msb of the data. the rwbit8_xx indicates the presence of a km.n control character in the receive data byte. only rwbit8_xx and rwd_xx inputs are stored in the fifo. during alignment process, ralign[3]_xx is used to synchronize multiple channels. if a channel is not in any alignment group, it will set the fifo-write-address to the beginning of the fifo, and will set the fifo-read-address to the middle of the fifo, at the ?st assertion of ralign[3]_xx after reset or after the resync command. the rx_fifo_min_xx register bits can be used to control the threshold for minimum unused buffer space in the alignment fifos between read and write pointers before over?w (ovfl) status is ?gged. the synchronization algorithm consists of a down counter which starts to count down by 1 from its initial value of 18 (decimal) when an alignment character from any channel within an alignment group has been received. once all the alignment char- acters within the alignment group have been received, the count is decremented by 2 until 0 is reached. data is then read from the fifos and output to the fpga. this algorithm is not repeated after multi-channel alignment has been achieved; resynchronization must be forced by toggling the appropriate fmpu_resync bit. ORT42G5 multi-channel alignment the ORT42G5 has a total of four channels. the incoming data of these channels can be synchronized in two ways or they can be independent of one other. two channels, c and d, within either serdes block can be aligned together to form a pair, as shown in figure 11. alternately, all four channels can be aligned together to form a com- munication channel with a bandwidth of 10 gbps, as shown in figure 12. individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. figure 11. dual channel alignment channel ad channel bc channel bd channel ac channel ad channel bc channel bd channel ac t 1 t 0 d ual alignment of channels ac and ad d ual a lignment of channels bc and bd lattice semiconductor orca ORT42G5 and ort82g5 data sheet 28 figure 12. four channel alignment of serdes blocks a and b ort82g5 multi-channel alignment the ort82g5 has a total of eight channels (four per serdes block). the incoming data of these channels can be synchronized in several ways or they can be independent of one other. two channels within a serdes block can be aligned together. channel a and b and/or channel c and d can form a pair as shown in figure 13. alternately, all four channels of a serdes block can be aligned together to form a communication channel with a bandwidth of 10 gbps as shown in figure 14. finally, the alignment can be extended across both serdes block to align all eight channels in ort82g5 as shown in figure 15. individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. figure 13. dual channel alignment figure 14. alignment of serdes quads a and b channel ad channel bc channel bd channel ac channel ad channel bc channel bd t 0 channel ac quad alignment of channels ac , ad , bc , and bd channel ab channel ac channel ad channel ba channel bb channel bc channel bd channel aa channel ab channel ac channel ad channel ba channel bb channel bc channel bd t 2 channel aa t 1 t 0 t 3 t win alignment of channels aa and ab t win a lignment of channels ac and ad twin alignment of channels ba and bb twin alignment of channels bc and bd channel ab channel ac channel ad channel ba channel bb channel bc channel bd channel aa channel ab channel ac channel ad channel ba channel bb channel bc channel bd t 1 t 0 channel aa quad alignment of channels aa , ab , ac , and ad quad alignment of channels ba , bb , bc , and bd lattice semiconductor orca ORT42G5 and ort82g5 data sheet 29 figure 15. alignment of all eight serdes channels. note that any channel within an alignment group can be removed from that alignment group by setting fmpu_str_en_xx to 0. the disabling of any channel(s) within an alignment group will not affect the operation of the remaining active channels. if the active channels are synchronized, that synchronization will be maintained and no data loss will occur. for every alignment group, there are both an ovfl and an oos status register bit. the ovfl bit is set when align- ment fifo over?w occurs. the oos bit is ?gged when the down counter in the synchronization algorithm has reached a value of 0 and alignment characters from all channels within an alignment group have not been received. in the memory map section for the ORT42G5 the bits indicating oos and ovfl are referred to as sync2_[a:b]_oos and sync4_oos and the bits indicating ovfl are sync2_[a:b]_ovfl and sync4_ovfl. in the memory map section for the ort82g5, the bits indicating oos and ovfl are referred to as sync2_[a1,a2,b1,b2]_oos, sync4_[a:b]_oos and sync8_oos and the bits indicating ovfl are sync2_[a1,a2,b1,b2]_ovfl, sync4_[a:b]_ovfl and sync8_ovfl. alignment can also be done between the receive channels on two ort82g5 devices. each of the two devices needs to provide its aligned k_ctrl or other alignment character to the other device, which will delay reading from a second alignment fifo until all channels requesting alignment on the current device and all channels requesting alignment on the other device are aligned (as indicated on the k_ctrl character). these second alignment fifos will be implemented in fpga logic on the ort82g5. this scheme also requires that the reference clock for both devices be driven by the same signal. xaui lane alignment function (lane deskew) in xaui mode, the receive section in each lane uses the /a/ code group to compensate for lane-to-lane skew. the mechanism restores the timing relationship between the 4 lanes by lining up the /a/ characters into a column. figure 16 shows the alignment of four lanes based on /a/ character. a minimum spacing of 16 code-groups implies that at least ?80 bits of skew compensation capability should be provided, which the devices signi?antly exceed. channel aa channel ab channel ac channel ad channel ba channel bb channel bc channel bd channel aa channel ab channel ac channel ad channel ba channel bb channel bc channel bd t 0 lattice semiconductor orca ORT42G5 and ort82g5 data sheet 30 figure 16. deskew lanes by aligning /a/ columns mixing half-rate, full-rate modes when channel alignment is enabled, all receive channels within an alignment group should be con?ured at the same rate. for example, in the ort82g5 channels aa, ab, can be con?ured for twin alignment and full-rate mode, while channels ac, ad that form an alignment group can be con?ured for half-rate mode. in block align- ment mode, each receive block can be con?ured in either half or full-rate mode. when channel alignment is disabled within a block, any receive channel within the block can be used in half-rate or full-rate mode. the clocking strategy for half-rate mode in both scenarios (channel alignment enabled or disabled) is described in the reference clocks and internal clock distribution sections later in this data sheet. multi-channel alignment con?uration ORT42G5 con?uration at startup, the legacy serdes channel logic must be powered down and removed from any multi-channel align- ment groups: setting bit 1 to one in registers at locations 30002, 30012, 30102, 30112, 30003, 30013, 30103 and 30113 pow- ers down the legacy logic. (note that the reset value for these bits is 0.) setting bits 4 and 5 to zero (reset condition) in the register at locations 30810 and 30910 removes the legacy logic from any alignment group. register settings for multi-channel alignment are shown in table 6. table 6. multichannel alignment modes to align two channels in serdes a: fmpu_synmode_a = 00001010 (register location 30811) to align two channels in serdes b: fmpu_synmode_b = 00001010 (register location 30911) to align all four channels: fmpu_synmode_a = 00001111 (register location 30811) register bits fmpu_synmode_[a:b][0:7] mode 00000000 no multichannel alignment. 00001010 twin channel alignment. 00001111 four channel alignment. lane 0 k rrkrk rkkrkrrk a lane 1 k rrkrk rkkrkrrk a lane 2 k rrkrk rkkrkrrk a lane 3 k rrkrk rkkrkrrk a lane 0 k rrkrk rkkrkrrk a lane 1 k rrkrk rkkrkrrk a lane 2 k rrkrk rkkrkrrk a lane 3 k rrkrk rkkrkrrk a lattice semiconductor orca ORT42G5 and ort82g5 data sheet 31 fmpu_synmode_b = 11111111 (register location 30911) to enable/disable multi-channel alignment of individual channels within a multi-channel alignment group: fmpu_str_en_xx = 1 enabled fmpu_str_en_xx = 0 disabled (register location 30810 and 30910, where xx is one of ac, ad, bc or bd.) to resynchronize a multichannel alignment group set the following bit to zero, and then set it to one. fmpu_resync4 for four channels, ac, ad, bc and bd. (register location 30a02, bit 2) fmpu_resync2a for dual channels, ac and ad. (register location 30820, bit 5) fmpu_resync2b for block channels, bc and bd. (register location 30920, bit 5) to resynchronize an independent channel (resetting the write and the read pointer of the fifo) set the following bit to zero, and then set it to one. fmpu_resync1_xx (register locations 30820 and 30920, bits 2 and 3, where xx is one of ac, ad, bc or bd). ort82g5 con?uration register settings for multi-channel alignment are shown in table 7. table 7. multi-channel alignment modes to align all eight channels: fmpu_synmode_a[a:d] = 11 fmpu_synmode_b[a:d] = 11 to align all four channels in serdes a: fmpu_synmode_a[a:d] = 01 to align two channels in serdes a: fmpu_synmode_a[a:b] = 10 for channel aa and ab fmpu_synmode_a[c:d] = 10 for channel ac and ad a similar alignment can be de?ed for serdes b. to enable/disable synchronization signal of individual channel within a multi-channel alignment group: fmpu_str_en_xx = 1 enabled fmpu_str_en_xx = 0 disabled where xx is one of a[a:d] and b[a:d]. to resynchronize a multi-channel alignment group set the following bit to zero, and then set it to one: fmpu_resync8 for eight channel a[a:d] and b[a:d] fmpu_resync4a for quad channel a[a:d] fmpu_resync2a1 for twin channel a[a:b] register bits fmpu_synmode_xx[0:1] mode 00 no multi-channel alignment. 10 twin channel alignment. 01 quad channel alignment. 11 eight channel alignment. note: where xx is one of a[a:d] and b[a:d]. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 32 fmpu_resync2a2 for twin channel a[c:d] fmpu_resync4b for quad channel b[a:d] fmpu_resync2b1 for twin channel b[a:b] fmpu_resync2b2 for twin channel b[c:d] to resynchronize an independent channel (resetting the write and the read pointer of the fifo) set the following bit to zero, and then set it to one: fmpu_resync1_xx ORT42G5 alignment sequence 1. follow steps 1, 2 and 3 in the start up sequence described in a later section. 2. initiate a serdes software reset by setting the swrst bit to 1 and then to 0. note that, any changes to the serdes con?uration bits should be followed by a software reset. 3. wait for 3 ms. refclk should be toggling by this time. during this time, con?ure the following registers. set the following bits in registers 30820, 30920: xaui_mode_xx-set to 1 for xaui mode or keep the default value of 0 if the fibre channel state machine was selected. enable channel alignment by setting fmpu_synmode bits in registers 30811, 30911. fmpu_synmode_xx. set to appropriate values for 2 or 4 channel alignment based on table 6. set rclksel[a:b] and tcksel[a:b] bits in register 30a00. rcksel[a:b]-choose clock source for 78 mhz rck78x (table 18). tcksel[a:b]-choose clock source for 78 mhz tck78x (table 17). send data on serial links. monitor the following status/alarm bits: monitor the following alarm bits in registers 30020, 30030, 30120, 30130. lki-pll_xx lock indicator. a 1 indicates that pll has achieved lock. monitor the following status bits in registers 30804, 30904 xauistat_xx - in xaui mode, they should be 10. monitor the following status bits in registers 30805, 30905 demuxwas_xx - they should be 1 indicating word alignment is achieved. ch24_syncxx - they should be 1 indicating channel alignment. this is cleared by resync. 4. write a 1 to the appropriate resync registers 30820, 30920 or 30a02. note that this assumes that the previous value of the resync bits are 0. the resync operation requires a rising edge. two writes are required to the resync bits: write a 0 and then write a 1. it is highly recommended to precede a resync with a word alignment, especially in situations where a disturbance in the receive serdes path can cause misalignment of data and oos indications without bringing the fc/xaui state machine to a loss of synch state. a word alignment is achieved by writing a 0 and then a 1 to the appropriate dowdalignxx bits in registers 30810/30910. check out-of-sync and fifo over?w status in registers 30814 (bank a). sync2_a_oos, sync2_a_ovfl - by 2 alignment. check out-of-sync status in registers 30914 (bank b). sync2_b_oos, sync2_b_ovfl - by 2 alignment. check out-of-sync status in registers 30a03. sync4_oos, sync4_ovfl - by 4 alignment. if out-of-sync bit is 1, then rewrite a 1 to the appropriate resync registers and monitor the oos bit again. if out of synchronization (oos) bit is 0 but ovfl bit is 1, then check if the rx_fifo_min value has been pro- lattice semiconductor orca ORT42G5 and ort82g5 data sheet 33 grammed to a value > 0. (default value is 0.) change the value to 0 and check the ovfl bit again. if oos and ovfl are 1, then rewrite a 1 to the appropriate resync registers. the resync operation requires a rising edge. two writes are required to the resync bits: write a 0 and then write a 1. ort82g5 alignment sequence 1. follow steps 1 and 2 in the start-up sequence described in a later section. 2. initiate a serdes software reset by setting the swrst bit to 1 and then to 0. note that any changes to the serdes con?uration bits should be followed by a software reset. 3. wait for 3 ms. refclk should be toggling by this time. during this time, con?ure the following registers. set the following bits in registers 30820, 30920 xaui_mode_xx-set to 1 for xaui mode or keep the default value of 0 if the fibre channel state machine was selected. enable channel alignment by setting fmpu_synmode bits in registers 30811, 30911. fmpu_synmode_xx. set to appropriate values for 2, 4, or 8 alignment based on table 7. set rclksel[a:b] and tcksel[a:b] bits in registers 30a00. rcksel[a:b] ?choose clock source for 78 mhz rck78x (table 18). tcksel[a:b] ?choose clock source for 78 mhz tck78x (table 17). send data on serial links. monitor the following status/alarm bits: monitor the following alarm bits in registers 30000, 30010, 30020, 30030, 30100, 30110, 30120, 30130. lki-pll_xx lock indicator. a 1 indicates that pll has achieved lock. monitor the following status bits in registers 30804, 30904: xauistat_xx - in xaui mode, they should be 10. monitor the following status bits in registers 30805, 30905 demuxwas_xx-they should be 1 indicating word alignment is achieved. ch248_syncxx-they should be 1 indicating channel alignment. this is cleared by resync. 4. write a 1 to the appropriate resync registers 30820, 30920 or 30a02. note that this assumes that the previous value of the resync bits are 0. the resync operation requires a rising edge. two writes are required to the resync bits: write a 0 and then write a 1. it is highly recommended to precede a resync with a word alignment, especially in situations where a disturbance in the receive serdes path can cause misalignment of data and oos indications without bringing the fc/xaui state machine to a loss of synch state. a word alignment is achieved by writing a 0 and then a 1 to the appropriate dowdalignxx bits in registers 30810/30910. check out-of-sync and fifo over?w status in registers 30814 (bank a). sync4_a_oos, sync4_a_ovfl-by 4 alignment. sync2_a2_oos, sync_a2_ovfl or sync2_a1_oos, sync2_a1_ovfl-by 2 alignment. check out-of-sync status in registers 30914 (bank b). sync4_b_oos, sync4_b_ovfl-by 4 alignment. sync_b2_oos, sync2_b2_ovfl or sync2_b1_oos, sync_b1_ovfl-by 2 alignment. check out-of-sync status in register 30a03 sync8_oos, sync8_ovfl-by 8 alignment. if out-of-sync bit is 1, then rewrite a 1 to the appropriate resync registers and monitor the oos bit again. if out of synchronization (oos) bit is 0 but ovfl bit is 1, then check if the rx_fifo_min value has been programmed to a value > 0. (default value is 0.) change the value to 0 and check the ovfl bit again. if oos and ovfl are 1, then rewrite a 1 to the appropriate resync registers. the resync operation requires a rising edge. two writes are required to the resync bits: write a 0 and then write a 1. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 34 embedded core/fpga interface this block provides the data formatting and receive data and clock signal transfers between the embedded core and the fpga logic. there are also control and status registers in the fpga portion of the chip which contain bits to control the receive logic and to record status. these are described in later sections of this data sheet and com- municate with the core using the system bus. the demultiplexed, receive word outputs to the fpga are shown in figure 6. these are each 40 bits wide. there are eight of these interfaces, one for each serdes channel. each consist of four groups of 10-bit data or four groups of decoded information depending on setting of 8b10br_xx control register bits. each 10-bit group of decoded information includes 8 bits of data and a 1 bit k_ctrl indicator derived from the received data and a tenth bit of status information. the function of the tenth bit varies from group to group and includes code violation, out of synchronization (oos) indicators and the ch24_sync24_xx and ch248_sync_xx status bits. ch24_sync or ch248_sync_xx indicates the status of multi-channel alignment of channel xx and are high when the count for the multi-channel alignment block reaches zero regardless of whether or not multi-channel alignment is successful. the mapping of the 10-bit groups to the mrwd_xx[39:0] bits output to the fpga logic is summarized in table 8. the various functions of the bits that vary from channel to channel, i.e., bits 29 and 19, are also described in table 9 and table 10. table 8. de?ition of bits of mrwdxx[39:0] bit index 8b10br=0 8b10br=1 nochalgn[a:b]=1 cv_selxx=0 nochalgn[a:b]=1 cv_selxx=1 nochalgn[a:b]=0 cv_selxx=1 39 bit 9 of 10-bit data 3 cv_xx3, code violation, byte 3 see table 9 and table 10 38 bit 8 of 10-bit data 3 k_ctrl for byte 3 k_ctrl for byte 3 37 bit 7 of 10-bit data 3 bit 7 of byte3 bit 7 of byte3 36 bit 6 of 10-bit data 3 bit 6 of byte 3 bit 6 of byte 3 35 bit 5 of 10-bit data 3 bit 5 of byte 3 bit 5 of byte 3 34 bit 4 of 10-bit data 3 bit 4 of byte 3 bit 4 of byte 3 33 bit 3 of 10-bit data 3 bit 3 of byte 3 bit 3 of byte 3 32 bit 2 of 10-bit data 3 bit 2 of byte 3 bit 2 of byte 3 31 bit 1of 10-bit data 3 bit 1 of byte 3 bit 1 of byte 3 30 bit 0 of 10-bit data 3 bit 0 of byte 3 bit 0 of byte 3 29 bit 9 of 10-bit data 2 cv_xx2, code violation, byte 2 see table 9 and table 10 28 bit 8 of 10-bit data 2 k_ctrl for byte 2 k_ctrl for byte 2 27 bit 7 of 10-bit data 2 bit 7 of byte 2 bit 7 of byte 2 26 bit 6 of 10-bit data 2 bit 6 of byte 2 bit 6 of byte 2 25 bit 5 of 10-bit data 2 bit 5 of byte 2 bit 5 of byte 2 24 bit 4 of 10-bit data 2 bit 4 of byte 2 bit 4 of byte 2 23 bit 3 of 10-bit data 2 bit 3 of byte 2 bit 3 of byte 2 22 bit 2 of 10-bit data 2 bit 2 of byte 2 bit 2 of byte 2 21 bit 1 of 10-bit data 2 bit 1 of byte 2 bit 1 of byte 2 20 bit 0 of 10-bit data 2 bit 0 of byte 2 bit 0 of byte 2 19 bit 9 of 10-bit data 1 cv_xx1, code violation, byte 1 see table 9 and table 10 18 bit 8 of 10-bit data 1 k_ctrl for byte 1 k_ctrl for byte 1 17 bit 7 of 10-bit data 1 bit 7 of byte 1 bit 7 of byte 1 16 bit 6 of 10-bit data 1 bit 6 of byte 1 bit 6 of byte 1 15 bit 5 of 10-bit data 1 bit 5 of byte 1 bit 5 of byte 1 14 bit 4 of 10-bit data 1 bit 4 of byte 1 bit 4 of byte 1 13 bit 3 of 10-bit data 1 bit 3 of byte 1 bit 3 of byte 1 lattice semiconductor orca ORT42G5 and ort82g5 data sheet 35 table 9. de?ition of status bits of mrwdxx that vary for different channels for the ORT42G5 in the ORT42G5, sync2_[a, b]_oos and sync4_oos signals can be used with ch24_sync_xx to determine if the desired multi-channel alignment was successful. if, when ch24_sync_xx goes high with the corresponding oos signal remaining low, the data being transferred across the core/fpga interface is correctly aligned between channels. note that only the signals corresponding to the selected alignment mode will be meaningful. 12 bit 2 of 10-bit data 1 bit 2 of byte 1 bit 2 of byte 1 11 bit 1 of 10-bit data 1 bit 1 of byte 1 bit 1 of byte 1 10 bit 0 of 10-bit data 1 bit 0 of byte 1 bit 0 of byte 1 09 bit 9 of 10-bit data 0 cv_xx0, code violation, byte 0 vl (connected to ground) 08 bit 8 of 10-bit data 0 k_ctrl for byte 0 k_ctrl for byte 0 07 bit 7 of 10-bit data 0 bit 7 of byte 0 bit 7 of byte 0 06 bit 6 of 10-bit data 0 bit 6 of byte 0 bit 6 of byte 0 05 bit 5 of 10-bit data 0 bit 5 of byte 0 bit 5 of byte 0 04 bit 4 of 10-bit data 0 bit 4 of byte 0 bit 4 of byte 0 03 bit 3 of 10-bit data 0 bit 3 of byte 0 bit 3 of byte 0 02 bit 2 of 10-bit data 0 bit 2 of byte 0 bit 2 of byte 0 01 bit 1 of 10-bit data 0 bit 1 of byte 0 bit 1 of byte 0 00 bit 0 of 10-bit data 0 bit 0 of byte 0 bit 0 of byte 0 channel index bit index name description all 39 ch24_syncxx multi-channel alignment attempt complete if 1 ac 29 cv_ac_or code violation in one or more of the received 10-bit groups for channel ac ac 19 sync2_a_oos dual channel synchronization of channels ac and ad not successful if 1 ad 29 cv_ad_or code violation in one or more of the received 10-bit groups for channel ad ad 19 sync4_oos four channel synchronization not successful if 1 bc 29 cv_bc_or code violation in one or more of the received 10-bit groups for channel bc bc 19 sync2_b_oos dual channel synchronization of channels bc and bd not successful if 1 bd 29 cv_bd_or code violation in one or more of the received 10-bit groups for channel bd bd 19 sync4_oos eight channel synchronization not successful if 1 table 10. de?ition of status bits of mrwdxx that vary for different channels for the ort82g5 channel index bit index name description all 39 ch248_syncxx multi-channel alignment attempt complete if 1 aa 29 cv_aa_or code violation in one or more of the received 10-bit groups for channel aa aa 19 sync2_a1_oos dual channel synchronization of channels aa and ab not successful if 1 ab 29 cv_ab_or code violation in one or more of the received 10-bit groups for channel ab ab 19 sync4_a_oos quad channel synchronization of serdes quad a not successful if 1 ac 29 cv_ac_or code violation in one or more of the received 10-bit groups for channel ac ac 19 sync2_a2_oos dual channel synchronization of channels ac and ad not successful if 1 ad 29 cv_ad_or code violation in one or more of the received 10-bit groups for channel ad ad 19 sync8_oos eight channel synchronization not successful if 1 table 8. de?ition of bits of mrwdxx[39:0] (continued) bit index 8b10br=0 8b10br=1 nochalgn[a:b]=1 cv_selxx=0 nochalgn[a:b]=1 cv_selxx=1 nochalgn[a:b]=0 cv_selxx=1 lattice semiconductor orca ORT42G5 and ort82g5 data sheet 36 for the ort82g5, the sync2_[a1,a2,b1,b2]_oos, sync4_[a:b]_oos,and sync8_oos signals can be used with ch248_sync_xx to determine if the desired multi-channel alignment was successful. if, when ch248_sync_xx goes high the corresponding oos signal remains low, the data being transferred across the core/fpga interface is correctly aligned between channels. note that only the signals corresponding to the selected alignment mode will be meaningful. for both devices, the code violation signals will only be valid if the corresponding cv_selxx = 1. (if 8b10br=0, cv_sel should also be zero. the cv_xx_or signals are obtained by oring four code violation signals from the 1:4 demux block. these are primarily indicators of received signal quality since a single code violation will not force a loss of sync (los) state in the word alignment state machines. since these signals come from the demux block, if multi-channel alignment is enabled, the code violation signals correspond to data that must still be multi- channel aligned. hence these signals provide advance noti?ation of detected violations in data that will appear at the core/fpga interface several clock cycles later. the exact number of clock cycles that the data is delayed depends on the skew between the incoming data for the different channels. transceiver fpga/embedded core signals table 12 summarizes the interface signals between the fpga logic and the core. in the table, an input refers to a signal ?wing into the embedded core and an output refers to a signal ?wing out of the embedded core. table 11. transceiver embedded core/fpga interface signal description for the ORT42G5 ba 29 cv_ba_or code violation in one or more of the received 10-bit groups for channel ba ba 19 sync2_b1_oos dual channel synchronization of channels ba and bb not successful if 1 bb 29 cv_bb_or code violation in one or more of the received 10-bit groups for channel bb bb 19 sync4_b_oos quad channel synchronization of serdes quad b not successful if 1 bc 29 cv_bc_or code violation in one or more of the received 10-bit groups for channel bc bc 19 sync2_b2_oos dual channel synchronization of channels bc and bd not successful if 1 bd 29 cv_bd_or code violation in one or more of the received 10-bit groups for channel bd bd 19 sync8_oos eight channel synchronization not successful if 1 fpga/embedded core interface signal name (xx = [ac, ad, bc or bd]) input (i) to or output (o) from core signal description transmit path signals twdxx[31:0] i transmit data ?channel xx. tcommaxx[3:0] i transmit comma character ?channel xx. tbit9xx[3:0] i transmit force negative disparity ?channel xx tsys_clk_xx i transmit low-speed clock to the fpga ?channel xx tck78[a:b] o transmit low-speed clock to the fpga ?serdes quad [a:b]. receive path signals mrwdxx[39:0] o receive data ?channel xx (see table 8 and table 9). rwckxx o low-speed receive clock?hannel xx. rck78[a:b] o receive low-speed clock to fpga?erdes quad [a:b]. rsys_clk_a2 i low-speed receive fifo clock for channels ac, ad rsys_clk_b2 i low-speed receive fifo clock for channels bc, bd cv_selxx i enable detection of code violations in the incoming data sys_rst_n i synchronous reset of the channel alignment blocks. table 10. de?ition of status bits of mrwdxx that vary for different channels for the ort82g5 (continued) channel index bit index name description lattice semiconductor orca ORT42G5 and ort82g5 data sheet 37 table 12. transceiver embedded core/fpga interface signal description for the ort82g5 reference clocks and internal clock distribution reference clock requirements there are two pairs of reference clock inputs on the ORT42G5 and ort82g5. the differential reference clock is distributed to all channels in a block. each channel has a differential buffer to isolate the clock from the other chan- nels. the input clock is preferably a differential signal; however, the device can operate with a single-ended input. the input reference clock directly impacts the transmit data eye, so the clock should have low jitter. in particular, jit- ter components in the dc to 5 mhz range should be minimized. the required electrical characteristics for the refer- ence clock are given in table 38. note: in sections of this data sheet, the differential clocks are simply referred to as the reference clock as refclk_[a:b]. synthesized and recovered clocks the serdes embedded core block contains its own dedicated plls for transmit and receive clock generation. the user provides a reference clock of the appropriate frequency, as described in the previous section. the trans- mitter pll uses the refclk_[a,b] inputs to synthesize the internal high-speed serial bit clocks. the receiver plls extract the clock from the serial input data and retime the data with the recovered clock. the receive pll for each channel has two modes of operation - lock to reference and lock to data with retiming. when no data or invalid data is present on the hdinp_xx and hdinn_xx pins, the receive vco will not lock to data and its frequency can drift outside of the nominal ?50 ppm range. under this condition, the receive pll will lock to refclk_[a,b] for a ?ed time interval and then will attempt to lock to receive data. the process of attempting to lock to data, then locking to clock will repeat until valid input data exists. there is also a control register bit per channel to force the receive pll to always lock to the reference clock. the high-speed transmit and receive serial data links can run at 0.6 to 3.7 gbps, depending on the frequency of the reference clock and the state of the control bits from the internal transmit control register. the interface to the seri- alizer/deserializer block runs at 1/10th the bit rate of the data lane. additionally, the mux/demux logic converts the fpga/embedded core interface signal name xx=... line remain (xx = [aa, ..., bd] input (i) to or output (o) from core signal description transmit path signals twdxx[31:0] i transmit data ?channel xx. tcommaxx[3:0] i transmit comma character ?channel xx. tbit9xx[3:0] i transmit force negative disparity ?channel xx tsys_clk_xx i transmit low-speed clock to the fpga ?channel xx tck78[a:b] o transmit low-speed clock to the fpga ?serdes quad [a:b]. receive path signals mrwdxx[39:0] o receive data ?channel xx (see table 8 and table ). rwckxx o low-speed receive clock?hannel xx. rck78[a:b] o receive low-speed clock to fpga?erdes quad [a:b]. rsys_clk_a1 i low-speed receive fifo clock for channels aa, ab rsys_clk_a2 i low-speed receive fifo clock for channels ac, ad rsys_clk_b1 i low-speed receive fifo clock for channels ba, bb rsys_clk_b2 i low-speed receive fifo clock for channels bc, bd cv_selxx i enable detection of code violations in the incoming data sys_rst_n i synchronous reset of the channel alignment blocks. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 38 data rate and bit-width so the fpga core can run at 1/4th this frequency which gives a range of 15 to 92.5 mhz for the data in and out of the fpga. internal clock signals at the fpga/core interface for the ORT42G5 there are several clock signals de?ed at the fpga/embedded core interface in addition to the external reference clock for each serdes block. all of the ORT42G5 clock signals are shown in figure 17 and are described follow- ing the ?ure. figure 17. ORT42G5 clock signals (high speed serial i/o also shown) refclkp_[a:b], refclkn_[a:b]: these are the differential reference clocks provided to the ORT42G5 device as described earlier. they are used as the reference clock for both tx and rx paths. for operation of the serial links at 3.125 gbps, the reference clocks will be at a frequency of 156.25 mhz. rwck[ac, ad, bc, bd]: these are the low-speed receive clocks from the embedded core to the fpga across the core-fpga interface. these are derived from the recovered low-speed complementary clocks from the serdes blocks. rwckac belongs to channel ac, rwckbc belongs to channel bc and so on. with a reference clock input of 156.25 mhz, these clocks operate at 78.125 mhz. rck78[a:b]: these are muxed outputs of rwcka[c or d] and rwckb[c or d] respectively. with a reference clock input of 156.25 mhz, these clocks operate at 78.125 mhz. rsys_clk_[a:b]2 these clocks are inputs to the serdes blocks a and b respectively from the fpga. these are used by each channel as the read clock to read received data from the alignment fifo within the embedded core. clock rsys_clk_a2 is used by channels in the serdes block a and rsys_clk_b2 by channels in the serdes block b. to guarantee that there is no over?w in the alignment fifo, it is an absolute requirement that the write and read clocks be frequency locked within 0 ppm. examples of how to achieve this are shown in the later section on recommended board-level clocking. fpga logic common logic, block a channel ac channel ad rck78a tck78a rsys_clk_a2 tsys_clk_ac rwckac rwckac tsys_clk_ad refclk[p:n]_a 2 hdin[p:n]_ad hdout[p:n]_ad 2 2 hdout[p:n]_ac 2 hdin[p:n]_ac 2 tck78a backplane serial link common logic, block b channel bc channel bd rck78b tck78b rsys_clk_b2 tsys_clk_bc rwckbc rwckbd tsys_clk_bd refclk[p:n]_b 2 hdin[p:n]_bd hdout[p:n]_bd 2 2 hdout[p:n]_bc 2 hdin[p:n]_bc 2 lattice semiconductor orca ORT42G5 and ort82g5 data sheet 39 tck78[a:b]: this is a muxed output from the core to the fpga across the core-fpga interface of one of the 2 transmit ser- des clocks per block operating at up to 92.5 mhz in the embedded core. there is one clock output per serdes block. tsys_clk[ac, ad, bc, bd]: these clocks are inputs to the serdes block a and b respectively from the fpga. these are used by each chan- nel to control the timing of the transmit data path. to guarantee correct transmit operation theses clocks must be frequency locked within 0 ppm to tck78[a:b]. transmit and receive clock rates table 13 shows typical relationship between the data rates, the reference clock, the transmit tck78[a:b] clock and the receive rck78[a:b] clock. the selection of full-rate or half-rate for a given reference clock speed is set by bits in the transmit and receive control registers and can be set per channel. table 13. transmit data and clock rates besides taking in a tsys_clk_xx from the fpga logic for each channel, the transmit path logic sends back a clock of the same frequency, but arbitrary phase. this clock, tck78[a:b], is derived from the mux block of one of the 2 channels in its serdes block. the mux blocks provide the potential source for tck78[a:b] by a divide-by-4 of the serdes stbc311xs clock used in synchronizing the transmit data words in the stbc311xx clock domain. the stbc311xx clocks are internal to the core and are not brought across the core/fpga interface the receiver section receives high-speed serial data at its differential cml input port and sends in to the clock and data recovery (cdr) block. the cdr block then generates a recovered clock (rwckxx) and retimes the data. thus, the recovered receive clocks are asynchronous between channels. transmit clock source selection the tcksel[a:b] bit select the source channel of tck78[a:b]. the selection of the source for tck78[a:b] is con- trolled by this bit as shown in table 14. table 14. tck78[a:b] source selection recommended transmit clock distribution for the ORT42G5 as an example of the recommended clock distribution approach, tsys_clk_a[c or d] can be sourced by tck78a as shown in figure 18 if the transmit line rate are common for both channels in a block. similar clocking would be used for block b. data rate reference clock tck78[a: b] and rck78[a:b] clocks rate of channel selected as clock source 0.6 gbps 60 mhz 15 mhz half 1.0 gbps 100 mhz 25 mhz half 1.25 gbps 125 mhz 31.25 mhz half 2.0 gbps 100 mhz 50 mhz full 2.5 gbps 125 mhz 62.5 mhz full 3.125 gbps 156 mhz 78 mhz full 3.7 gbps 185 mhz 92.5 mhz full tcksel[a:b] clock source 0 channel c 1 channel d lattice semiconductor orca ORT42G5 and ort82g5 data sheet 40 figure 18. transmit clocking for a single block (similar connections would be used for block b) if the transmit line rate is mixed between half and full rate among the channels, then the scheme shown in figure 19 can be used. the ?ure shows tsys_clk_ac being sourced by tck78a and tsys_clk_ad being sourced by tck78a/2 (the division is done in fpga logic). similar clocking would be used for block b. figure 19. mixed rate transmit clocking for a single block (similar connections would be used for block b) receive clock source selection and recommended clock distribution in the receive path, one clock per block of two channels, called rck78[a:b], is sent to the fpga logic. the control register bits rcksel[a:b] is used to select the clock source for these clocks. the selection of the source for rck78[a:b] is controlled by this bit as shown in table 15. table 15. rck78[a:b] source selection in the receive channel alignment bypass mode the data and recovered clocks for the four channels are indepen- dent. the data for each channel are synchronized to the recovered clock from that channel. figure 21 shows the recommended receive clocking for a single block. rcksel[a:b] clock source 0 channel c 1 channel d common logic, block a channel ac channel ad refclk[p:n]_a 2 156.25 mhz tck78a tsys_clk_ac tsys_clk_ad fpga logic all clocks at 78.125 mhz two channels of 3.125 gbps outgoing serial data common logic, block a channel ac channel ad refclk[p:n]_a 2 100 mhz tck78a tsys_clk_ac tsys_clk_ad fpga logic one channel of 2.0 gbps (full-rate) and one channel of 1.0 gbps (half-rate) outgoing serial data 2 25 mhz 50 mhz channel ac selected as clock source lattice semiconductor orca ORT42G5 and ort82g5 data sheet 41 figure 20. receive clocking for a single block (similar connections would be used for block b) the receive channel alignment bypass mode allows mixing of half and full line rates among the channels, as shown in figure 21. the ?ure shows channel ac con?ured in full rate mode at 2.0 gbps. channel ad con?ured in half- rate mode at 1.0 gbps. the receive alignment fifo per channel cannot be used in this mode. figure 21. receive clocking for mixed line rates each serdes block can also be con?ured for any line rate (0.6 to 3.7 gbps), since each block has its own refer- ence clock input pins. multi-channel alignment clocking strategies for the ORT42G5 the data on the four channels in the ORT42G5 can be independent of each other or can be synchronized in two different ways. for example, two channels within a serdes block can be aligned together, channel c and channel d. alternatively, all four channels in a serdes block can be aligned together to form a communication channel with a bandwidth of 10 gbps. individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. clocking strategies for these various modes are described in the following para- graphs. for dual alignment both channels must be sourced by the same clock. either rwckac or rwckad can be con- nected to rsys_clk_a2. a clocking example for dual alignment is shown in figure 22. common logic, block a channel ac channel ad refclk[p:n]_a 2 156.25 mhz rck78a rwckac rwckad rsys_clk_a2 fpga logic two channels of 3.125 gbps incoming serial data 78.125 mhz all recovered clocks at 78.125 mhz common logic, block a channel ac channel ad refclk[p:n]_a 2 100 mhz rck78a rwckac fpga logic one channel of 2.0 gbps (full-rate) and one channel of 1.0 gbps (half-rate) incoming serial data 25 mhz rwckad 25 mhz or 50 mhz 50 mhz rsys_clk_a2 lattice semiconductor orca ORT42G5 and ort82g5 data sheet 42 figure 22. receive clocking for a dual alignment in a single block (similar connections would be used for block b) for quad alignment, either rck78a or rck78b can be used to source rsys_clk_[a:b]2 as shown in figure 23. figure 23. clocking for quad alignment common logic, block a channel ac channel ad refclk[p:n]_a 2 156.25 mhz tck78a rwckac rwckad rsys_clk_a2 fpga logic all clocks at 78.125 mhz two bidirectional channels of 3.125 gbps serial data tsys_clk_ad tsys_clk_ac rck78a common logic, block a channel ac channel ad refclk[p:n]_a 2 156.25 mhz tck78a rwckac rwckad rsys_clk_a2 fpga logic all clocks at 78.125 mhz tsys_clk_ad tsys_clk_ac rck78a four bidirectional channels of 3.125 gbps serial data common logic, block b channel bc channel bd refclk[p:n]_b 2 tck78b rwckbc rwckbd rsys_clk_b2 tsys_clk_bd tsys_clk_bc rck78b lattice semiconductor orca ORT42G5 and ort82g5 data sheet 43 internal clock signals at the fpga/core interface for the ort82g5 there are several clock signals de?ed at the fpga/embedded core interface in addition to the external reference clock for each serdes quad. all of the ort82g5 clock signals are shown in figure 24 and are described follow- ing the ?ure. figure 24. ort82g5 clock signals (high speed serial i/o also shown) refclkp_[a:b], refclkn_[a:b]: these are the differential reference clocks provided to the ort82g5 device as described earlier. they are used as the reference clock for both tx and rx paths. for operation of the serial links at 3.125 gbps, the reference clocks will be at a frequency of 156.25 mhz. rwck[aa:bd]: these are the low-speed receive clocks from the embedded core to the fpga across the core-fpga interface. these are derived from the recovered low-speed complementary clocks from the serdes blocks. rwck_aa belongs to channel aa, rwck_ab belongs to channel ab and so on. with a reference clock input of 156.25 mhz, these clocks operate at 78.125 mhz. rck78[a:b]: these are muxed outputs of rwcka[a:d] and rwckb[b:d] respectively. with a reference clock input of 156.25 mhz, these clocks operate at 78.125 mhz. fpga logic common logic, quad a channel aa channel ab channel ad channel ac common logic, quad b channel ba channel bb channel bd channel bc rck78a tck78a rsys_clk_a1 tsys_clk_aa rwckaa rwckab tsys_clk_ab rwckac tsys_clk_ac rsys_clk_a2 tsys_clk_ad rwckad rck78b tck78b rsys_clk_b1 tsys_clk_ba rwckba rwckbb tsys_clk_bb rsys_clk_b2 rwckbd rwckbc tsys_clk_bc tsys_clk_bd refclk[p:n]_a 2 hdin[p:n]_ac 2 hdout[p:n]_ad hdin[p:n]_ad 2 hdout[p:n]_ac hdout[p:n]_ab 2 hdin[p:n]_ab 2 hdout[p:n]_aa 2 hdin[p:n]_aa 2 2 2 refclk[p:n]_b hdin[p:n]_bc 2 hdin[p:n]_bd 2 2 hdin[p:n]_bb 2 2 hdin[p:n]_ba 2 2 2 hdout[p:n]_ba hdout[p:n]_bb hdout[p:n]_bc hdout[p:n]_bd 2 tck78a backplane serial link lattice semiconductor orca ORT42G5 and ort82g5 data sheet 44 rsys_clk_[a:b][1:2] these clocks are inputs to the serdes quad block a and b respectively from the fpga. these are used by each channel as the read clock to read received data from the alignment fifo within the embedded core. clocks rsys_clk_a[1:2] are used by channels in the serdes quad block a and rsys_clk_b[1:2] by channels in the serdes quad block b. to guarantee that there is no over?w in the alignment fifo, it is an absolute requirement that the write and read clocks be frequency locked within 0 ppm. examples of how to achieve this are shown in the later section on recommended board-level clocking. tck78[a:b]: this is a muxed output from the core to the fpga across the core-fpga interface of one of the 4 transmit ser- des clocks per quad operating at up to 92.5 mhz in the embedded core. there is one clock output per serdes quad block. tsys_clk[aa,?d]: these clocks are inputs to the serdes quad block a and b respectively from the fpga. these are used by each channel to control the timing of the transmit data path. to guarantee correct transmit operation theses clocks must be frequency locked within 0 ppm to tck78[a:b]. transmit and receive clock rates table 16 shows the typical relationship between the data rates, the reference clock, the transmit tck78[a:b] clock and the receive rck78[a:b] clock. the selection of full-rate or half-rate for a given reference clock speed is set by bits in the transmit and receive control registers and can be set per channel. table 16. transmit data and clock rates besides taking in a tsys_clk_xx from the fpga logic for each channel, the transmit path logic sends back a clock of the same frequency, but arbitrary phase. this clock, tck78[a:b], is derived from the mux block of one of the 4 channels in its serdes quad. the mux blocks provide the potential source for tck78[a:b] by a divide-by-4 of the serdes stbc311xs clock used in synchronizing the transmit data words in the stbc311xx clock domain. the stbc311xx clocks are internal to the core and are not brought across the core/fpga interface. the receiver section receives high-speed serial data at its differential cml input port and sends in to the clock and data recovery (cdr) block. the cdr block then generates a recovered clock (rwckxx) and retimes the data. thus, the recovered receive clocks are asynchronous between channels. transmit clock source selection the tcksel[0:1][a:b] bits select the source channel of tck78[a:b]. the selection of the source for tck78[a:b] is controlled by these bits as shown in table 17. data rate reference clock tck78[a: b] and rck78[a:b] clocks rate of channel selected as clock source 0.6 gbps 60 mhz 15 mhz half 1.0 gbps 100 mhz 25 mhz half 1.25 gbps 125 mhz 31.25 mhz half 2.0 gbps 100 mhz 50 mhz full 2.5 gbps 125 mhz 62.5 mhz full 3.125 gbps 156 mhz 78 mhz full 3.7 gbps 185 mhz 92.5 mhz full lattice semiconductor orca ORT42G5 and ort82g5 data sheet 45 table 17. tck78[a:b] source selection recommended transmit clock distribution for the ort82g5 as an example of the recommended clock distribution approach, tsys_clk_a[a:d] can be sourced by tck78a as shown in figure 25 if the transmit line rate are common for all four channels in a quad. similar clocking would be used for quad b. figure 25. transmit clocking for a single block (similar connections would be used for block b) if the transmit line rate is mixed between half and full rate among the channels, then the scheme shown in figure 26 can be used. the ?ure shows tsys_clk_aa and tsys_clk_ab being sourced by tck78a and tsys_clk_ac and tsys_clk_ad being sourced by tck78a/2 (the division is done in fpga logic). similar clocking would be used for quad b. tcksel0 tcksel1 clock source 0 0 channel a 1 0 channel b 0 1 channel c 1 1 channel d common logic, quad a channel aa channel ab channel ad channel ac refclk[p:n]_a 2 156.25 mhz tck78a tsys_clk_aa tsys_clk_ac tsys_clk_ab tsys_clk_ad fpga logic all clocks at 78.125 mhz four channels of 3.125 gbps outgoing serial data lattice semiconductor orca ORT42G5 and ort82g5 data sheet 46 figure 26. mixed rate transmit clocking for a single block (similar connections would be used for block b) receive clock source selection and recommended clock distribution in the receive path, one clock per bank of four channels, called rck78[a:b], is sent to the fpga logic. the control register bits rcksel[0:1][a:b] are used to select the clock source for these clocks. the selection of the source for rck78[a:b] is controlled by these bits as shown in table 18. table 18. rck78[a:b] source selection in the receive channel alignment bypass mode the data and recovered clocks for the eight channels (four per ser- des quad) are independent. the data for each channel are synchronized to the recovered clock from that channel. figure 27. - receive clocking for a single quad (similar connections would be used for quad b) rcksel0 rcksel1 clock source 0 0 channel a 1 0 channel b 0 1 channel c 1 1 channel d common logic, quad a channel aa channel ab channel ad channel ac refclk[p:n]_a 2 100 mhz tck78a tsys_clk_aa tsys_clk_ac tsys_clk_ab tsys_clk_ad fpga logic two channels of 2.0 gbps (full-rate) outgoing serial data channel aa selected as clock source 50 mhz 2 25 mhz two channels of 1.0 gbps (half-rate) outgoing serial data common logic, quad a channel aa channel ab channel ad channel ac refclk[p:n]_a 2 156.25 mhz rck78a rwckaa rwckac rsys_clk_a1 rsys_clk_a2 fpga logic four channels of 3.125 gbps incoming serial data 78.125 mhz rwckab rwckad all recovered clocks at 78.125 mhz lattice semiconductor orca ORT42G5 and ort82g5 data sheet 47 the receive channel alignment bypass mode allows mixing of half and full line rates among the channels, as shown in figure 28. the ?ure shows channel pair aa and ab con?ured in full rate mode at 2.0 gbps. channel pair ac and ad are con?ured in half-rate mode at 1.0 gbps. figure 28. receive clocking for mixed line rates as noted in the caption of figure 28, each quad can be con?ured in any line rate (0.6 to 3.7 gbps), since each quad has its own reference clock input pins. the receive alignment fifo per channel cannot be used in this mode. multi-channel alignment clocking strategies for the ort82g5 the data on the eight channels (four per serdes quad) in the ort82g5 can be independent of each other or can be synchronized in several ways. for example, two channels within a serdes can be aligned together; channel a and b and/or channel c and d. alternatively, all four channels in a serdes quad can be aligned together to form a communication channel with a bandwidth of 10 gbps. finally, the alignment can be extended across both serdes quads to align all eight channels. individual channels within an alignment group can be disabled (i.e., powered down) without disrupting other channels. clocking strategies for these various modes are described in the following paragraphs. for dual alignment both twins within a quad can be sourced by clocks that are different from the other channels, however each pair of serdes must have the same clock. the channel pair aa and ab is driven on the low speed side by rsys_clk_a1 and the channel pair ac and ad are driven on the low speed side by rsys_clk_a2. either rwckaa or rwckab can be connected to rsys_clk_a1 and either rwckac or rwckad can be con- nected to rsys_clk_a2. a clocking example for dual alignment is shown in figure 29. common logic, quad a channel aa channel ab channel ad channel ac refclk[p:n]_a 2 100 mhz rck78a rwckaa rwckac rsys_clk_a1 rsys_clk_a2 fpga logic two channels of 2.0 gbps (full-rate) incoming serial data 25 mhz rwckab rwckad recovered clocks at 25 mhz or 50 mhz { recovered clocks at 50 mhz { two channels of 1.0 gbps (half-rate) incoming serial data lattice semiconductor orca ORT42G5 and ort82g5 data sheet 48 figure 29. receive clocking for a dual alignment in a single quad (similar connections would be used for quad b) for receive quad alignment, rsys_clk_[a1,b1] and rsys_clk_[a2,b2] can be tied together as shown for quad a and b in figure 30. in receive eight-channel alignment, either rck78a or rck78b can be used to source rsys_clk_[a1,a2] and rsys_clk_[b1,b2] as shown in figure 31. figure 30. clocking for quad alignment in a single quad (similar connections would be used for quad b) common logic, quad a channel aa channel ab channel ad channel ac refclk[p:n]_a 2 156.25 mhz rck78a rwckaa rwckac rsys_clk_a1 rsys_clk_a2 fpga logic two bidirectional channels of 3.125 gbps serial data rwckab rwckad all clocks at 78.125 mhz tck78a tsys_clk_aa tsys_clk_ab tsys_clk_ac tsys_clk_ad two bidirectional channels of 3.125 gbps serial data common logic, quad a channel aa channel ab channel ad channel ac refclk[p:n]_a 2 156.25 mhz rck78a rwckaa rwckac rsys_clk_a1 rsys_clk_a2 fpga logic four bidirectional channels of 3.125 gbps serial data rwckab rwckad all clocks at 78.125 mhz tck78a tsys_clk_aa tsys_clk_ab tsys_clk_ac tsys_clk_ad lattice semiconductor orca ORT42G5 and ort82g5 data sheet 49 figure 31. clocking for eight channel alignment reset operation the serdes block can be reset in one of three different ways as follows: on power up, using the hardware reset, or via the microprocessor interface. the power up reset process begins when the power supply voltage ramps up to approximately 80% of the nominal value of 1.5v. following this event, the device will be ready for normal operation after 3 ms. a hardware reset is initiated by making the pasb_resetn low for at least two microprocessor clock cycles. the device will be ready for operation 3 ms after the low to high transition of the pasb_resetn. this reset function affects all serdes channels and resets all microprocessor and internal registers and counters. using the software reset option, each channel can be individually reset by setting swrst (bit 2) to a logic 1 in the channel con?uration register. the device will be ready 3 ms after the swrst bit is deasserted. similarly, all four channels per quad serdes can be reset by setting the global reset bit gswrst. the device will be ready for nor- mal operation 3 ms after the gswrst bit is deasserted. note that the software reset option resets only serdes internal registers and counters. the microprocessor registers are not affected. it should also be noted that the embedded block cannot be accessed until after fpga con?uration is complete. fpga logic common logic, quad a channel aa channel ab channel ad channel ac common logic, quad b channel ba channel bb channel bd channel bc rck78a tck78a rsys_clk_a1 tsys_clk_aa rwckaa rwckab tsys_clk_ab rwckac tsys_clk_ac rsys_clk_a2 tsys_clk_ad rwckad rck78b tck78b rsys_clk_b1 tsys_clk_ba rwckba rwckbb tsys_clk_bb rsys_clk_b2 rwckbd rwckbc tsys_clk_bc tsys_clk_bd tck78a 2 refclk[p:n]_a 2 refclk[p:n]_b 156.25 mhz all clocks at 78.125 mhz eight bidirectional channels of 3.125 gbps serial data lattice semiconductor orca ORT42G5 and ort82g5 data sheet 50 start up sequence for the ORT42G5 the following sequence is required by the ORT42G5 device. for information required for simulation that may be dif- ferent than this sequence, see the ORT42G5 design kit. 1. initiate a hardware reset by making pasb_resetn low. keep this low during fpga con?uration of the device. the device will be ready for operation 3 ms after the low to high transition of pasb_resetn. 2. at startup, the legacy serdes channel logic must be powered down and removed from any multi-channel alignment groups: setting bit 1 to one in registers at locations 30002, 30012, 30102, 30112, 30003, 30013, 30103 and 30113 powers down the legacy logic. (note that the reset value for these bits is 0.) setting bits 4 and 5 to zero (reset condition) in the register at locations 30810 and 30910 removes the legacy logic from any alignment group. 3. con?ure the following serdes internal and external registers. note that after device initialization, all alarm and status bits should be read once to clear them. a subsequent read will provide the valid state. set the following bits in register 30800: ?bits lckrefn_[ac and ad] to 1, which implies lock to data. ?bits enbysync_[ac and ad] to 1 which enables dynamic alignment to comma. set the following bits in register 30801: ?bits loopenb_[ac and ad] to 1 if high-speed serial loopback is desired. set the following bits in register 30900: ?bits lckrefn_[bc and bd] to 1 which implies lock to data. ?bits enbysync_[bc and bd] to 1 which enables dynamic alignment to comma. set the following bits in register 30901: ?bits loopenb_[bc and bd] to 1 if high-speed serial loopback is desired. set the following bits in registers 30022, 30032, 30122, 30132: ?txhr set to 1 if tx half-rate is desired. ?8b10bt set to 1 if 8b10b encoding is desired. set the following bits in registers 30023, 30033, 30123, 30133: ?rxhr set to 1 if rx half-rate is desired. ?8b10br set to 1 if 8b10b decoding is desired. ?linksm set to 1 if the fibre channel state machine is desired. assert gswrst bit by writing 1 s to both serdes blocks. deassert gswrst bit by writing 0 s to both ser- des blocks. wait 3 ms. if higher speed serial loopback has been selected, the receive plls will use this time to lock to the new serial data. monitor the following alarm bits in registers 30020, 30030, 30120, 30130: ?lki, pll lock indicator. 1 indicates that pll has achieved lock. 4. if 8b/10b mode is enabled, enable link synchronization by periodically sending the following sequence three times: ?k28.5 d21.4 d21.5 d21.5 or any other idle ordered set (starting with a /comma/) in fc mode. ?/comma/ characters for the xaui state machine and /a/ characters for word and channel alignment in xaui mode. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 51 start up sequence for the ort82g5 the following sequence is required by the ort82g5 device. for information required for simulation that may be dif- ferent than this sequence, see the ort82g5 design kit. 1. initiate a hardware reset by making pasb_resetn low. keep this low during fpga con?uration of the device. the device will be ready for operation 3 ms after the low to high transition of pasb_resetn. 2. con?ure the following serdes internal and external registers. note that after device initialization, all alarm and status bits should be read once to clear them. a subsequent read will provide the valid state. set the fol- lowing bits in register 30800: ?bits lckrefn_[aa:ad] to 1, which implies lock to data. ?bits enbysync_[aa:ad] to 1 which enables dynamic alignment to comma. set the following bits in register 30801: ?bits loopenb_[aa:ad] to 1 if high-speed serial loopback is desired. set the following bits in register 30900: ?bits lckrefn_[ba:bd] to 1 which implies lock to data. ?bits enbysync_[ba:bd] to 1 which enables dynamic alignment to comma. set the following bits in register 30901: ?bits loopenb_[ba:bd] to 1 if high-speed serial loopback is desired. set the following bits in registers 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132: ?txhr set to 1 if tx half-rate is desired. ?8b10bt set to 1 set the following bits in registers 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133: ?rxhr set to 1 if rx half-rate is desired. ?8b10br set to 1. ?linksm set to 1 if the fibre channel state machine is desired. assert gswrst bit by writing two 1 s. deassert gswrst bit by writing two 0 s. wait 3ms. if higher speed serial loopback has been selected, the receive plls will use this time to lock to the new serial data. monitor the following alarm bits in registers 30000, 30010, 30020, 30030, 30100, 30110, 30120, 30130: ?lki, pll lock indicator. 1 indicates that pll has achieved lock. 3. if 8b/10b mode is enabled, enable link synchronization by periodically sending the following sequence three times: ?k28.5 d21.4 d21.5 d21.5 or any other idle ordered set (starting with a /comma/) in fc mode. ?/comma/ characters for the xaui state machine and /a/ characters for word and channel alignment in xaui mode. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 52 test modes in addition to the operational logic described in the preceding sections, the embedded core contains logic to sup- port various test modes - both for device validation and evaluation and for operating system level tests. the follow- ing sections discuss two of the test support logic blocks, supporting various loopback modes and serdes characterization. loopback testing loopback testing is performed by looping back (either internal to the embedded core, by con?uring the fpga logic or by external connections) transmitted data to the corresponding receiver inputs, or received data to the transmitter output. the loopback path may be either serial or parallel. in general, loopback tests can be classi?d as ?ear end or ?ar end. in ?ear end loopback (figure 32(a)), data is generated and checked locally, i.e. by logic on, or connection of, test equipment to the same card as the fpsc. in ?ar end loopback (figure 32(b)), the generating and checking functions are performed remotely, either by test equipment or a remote system card. figure 32. ?ear end vs. ?ar end loopback the loopback mode can also be characterized by the physical location of the loopback connection. there are three possible loopback modes supported by the embedded core logic: high-speed serial loopback at the cml buffer interface (near end) parallel loopback at the serdes boundary (far end) device under test (dut) cml buffer cml buffer hdin[p:n]_xx 2 non-functional embedded core fpga logic 40 mrwdxx[39:0] 32 4 4 receive transmit twdxx[31:0] tcommaxx[3:0] tbit9xx[3:0] hdout[p:n]_xx 2 data checking data generation n m { active (to eye diagram measurement or remote system card) test equipment or logic on local system card (a) ?ear end loopback high speed serial loopback connection device under test (dut) data generation data checking 2 2 hdin[p:n]_xx hdout[p:n]_xx { n m non-functional active (to logic on local system card) (b) ?ar end loopback fpga logic 40 mrwdxx[39:0] receive 4 4 transmit twdxx[31:0] tcommaxx[3:0] tbit9xx[3:0] 32 de mux 8b/10b serdes cml buffer 8b/10b cml buffer serdes block parallel loopback connection serdes embedded core lattice semiconductor orca ORT42G5 and ort82g5 data sheet 53 parallel loopback at mux/demux boundary excluding serdes (near end) the three loopback modes are described in more detail in the following sections. as noted earlier, other specialized loopback modes can be obtained by con?uration of the fpga logic or by connections external to the fpsc. high-speed serial loopback at the cml buffer interface the high-speed serial loopback mode has the serial transmit signals looped back internally to the serial receive cir- cuitry. the internal loopback path is from the input connection to the transmit cml buffer to the output connection from the receive cml buffer. the data are sourced on the twdxx[31:0], tcommaxx[3:0] and tbit9xx[3:0] signal lines and received on the mrwdxx[39:0] signal lines. the serial loopback path does not include the high-speed input and output buffers. if testen_xx is set, the hdoutp_xx and hdoutn_xx outputs are active in this mode while the cml input buffers are powered down. the device is otherwise in its normal mode of operation. this mode is normally used for tests where the data source and destination are on the same card and is the basic loopback path shown earlier in figure 32(a). the data rate selection bits, txhr and rxhr, in the channel con?uration registers must be con?ured to carry the same value. table 19 and table 20 summarize the settings of the control interface register con?uration bits for high-speed serial loopback. table 19. high-speed serial loopback con?uration bit de?itions for the ORT42G5 table 20. high-speed serial loopback con?uration bit de?itions for the ort82g5 register address bit value bit name comments 30022, 30032, 30122, 30132 bit 0 = 0 or 1 txhr set to 0 or 1. txhr and rxhr bits must be set to the same value. bit 7 = 0 or 1 8b10bt set to 0 or 1. if set to 0, the 8b/10b encoder is excluded from the loopback path. the 8b/10b encoder and decoder selec- tion control bits must both be set to the same value. 30023, 30033, 30123, 30133 bit 0 = 0 or 1 rxhr set to 0 or 1. txhr and rxhr bits must be set to the same value. bit 3 = 0 or 1 8b10br set to 0 or 1. if set to 0, the 8b/10b decoder is excluded from the loopback path. the 8b/10b encoder and decoder selec- tion control bits must both be set to the same value. 30801, 30901 bit 2 = 1 (channel c) bit 3 = 1 (channel d) loopenb_xx set any of the bits 0-3 to 1 to do serial loopback on the corre- sponding channel.* the high speed serial outputs will not be active. *this test mode can also be set using testen_xx in place of loopenb_xx. in that case, test mode must be set to 00000. register address bit value bit name comments 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132 bit 0 = 0 or 1 txhr set to 0 or 1. txhr and rxhr bits must be set to the same value. bit 7 = 0 or 1 8b10bt set to 0 or 1. if set to 0, the 8b/10b encoder is excluded from the loopback path. the 8b/10b encoder and decoder selec- tion control bits must both be set to the same value. 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133 bit 0 = 0 or 1 rxhr set to 0 or 1. txhr and rxhr bits must be set to the same value. bit 3 = 0 or 1 8b10br set to 0 or 1. if set to 0, the 8b/10b decoder is excluded from the loopback path. the 8b/10b encoder and decoder selec- tion control bits must both be set to the same value. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 54 parallel loopback at the serdes boundary in this parallel loopback differential data are received at the hdinp_xx and hdinn_xx pins and are retransmitted at the hdoutp_xx and hdoutn_xx pins. the loopback path is at the interface between the serdes blocks and the mux and demux blocks and uses the parallel 10-bit buses at these interfaces (see figure 32b). the loopback connection is made such that the input signals to the tx serdes block is the same as the output signals from the rx serdes block. in this parallel loopback mode, the mrwdxx[39:0] signal lines remain active and the twdxx[31:0], tcommaxx[3:0] and tbit9xx[3:0] signal lines are not used. this mode is normally used for tests where serial test data is received from and transmitted to either test equipment or via a serial backplane to a remote card and is the basic loopback path shown earlier in figure 32(b). the data rate selection bits txhr and rxhr in the channel con?uration registers must be con?ured to carry the same value. also, the 8b/10b encoder and decoder are excluded from the loopback path by setting the 8b10bt and 8b10br con?uration bits to 0. table 21 and table 22 illustrate the control interface register con?uration for the parallel loopback. table 21. parallel loopback at the serdes boundary con?uration bit de?itions table 22. parallel loopback at the serdes boundary con?uration bit de?itions for the ort82g5 30801, 30901 bit 0 =1 (channel a) bit 1 = 1 (channel b) bit 2 = 1 (channel c) bit 3 = 1 (channel d) loopenb_xx set any of the bits 0-3 to 1 to do serial loopback on the corre- sponding channel.* the high speed serial outputs will not be active. *this test mode can also be set using testen_xx in place of loopenb_xx. in that case, test mode must be set to 00000. register address (hex) bit value bit name comments 30022, 30032, 30122, 30132 bit 0 = 0 or 1 txhr set to 0 or 1. txhr and rxhr bits must be set to the same value. bit 7 = 0 8b10bt set to 0 the 8b/10b encoder is excluded from the loopback path. the 8b/10b encoder and decoder selection control bits must both be set to 0. 30023, 30033, 30123, 30133 bit 0 = 0 or 1 rxhr set to 0 or 1. txhr and rxhr bits must be set to the same value. bit 3 = 0 8b10br set to 0.the 8b/10b decoder is excluded from the loopback path. the 8b/10b encoder and decoder selection control bits must both be set to 0. 30005, 30105 bit 7 = 1 gtesten set to 1 if the loopback is done globally on both channels. 30026, 30036, 30126, 30136 bits[4:0] testmode set to 00001 register address (hex) bit value bit name comments 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132 bit 0 = 0 or 1 txhr set to 0 or 1. txhr and rxhr bits must be set to the same value. bit 7 = 0 8b10bt set to 0 the 8b/10b encoder is excluded from the loopback path. the 8b/10b encoder and decoder selection control bits must both be set to 0. 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133 bit 0 = 0 or 1 rxhr set to 0 or 1. txhr and rxhr bits must be set to the same value. bit 3 = 0 8b10br set to 0.the 8b/10b decoder is excluded from the loopback path. the 8b/10b encoder and decoder selection control bits must both be set to 0. 30005, 30105 bit 7 = 1 gtesten set to 1 if the loopback is done globally on all four channels. 30006, 30016, 30026, 30036, 30106, 30116, 30126, 30136 bits[4:0] testmode set to 00001 register address bit value bit name comments lattice semiconductor orca ORT42G5 and ort82g5 data sheet 55 parallel loopback at mux/demux boundary, excluding serdes this is a low-frequency test mode used to test the mux/demux logic block. as with the mode described in the pre- vious section, the loopback path is at the interface between the serdes blocks and the mux and demux blocks and uses the parallel 10-bit buses at these interfaces (see figure 33). however, the loopback connection is made such that the output signals from the tx mux block are used as the input signals to the rx serdes block. in this loopback mode the mrwdxx[39:0], twdxx[31:0], tcommaxx[3:0] and tbit9xx[3:0] signal lines function normally and the high-speed serial input and output buffers are not used. use of this mode also requires con?uration of the fpga logic to connect the mrwdxx[39:0], twdxx[31:0], tcommaxx[3:0] and tbit9xx[3:0] signal lines to exter- nal pins. the basic loopback path is shown in figure 33. figure 33. parallel loopback at mux/demux boundary, excluding serdes this test mode is enabled by setting the pin ploop_test_enn to 0. pasb_testclk must be running in this mode at 4x frequency of rsys_clk[a2, b2] or tsys_clk_[ac, ad, bc, bd] for the ORT42G5 and rsys_clk[a1,a2,b1,b2] or tsys_clk_[aa, ab... bd] for the ort82g5. serdes characterization test mode (ort82g5 only) the serdes characterization mode is a test mode that allows for direct control and observation of the transmit and receive serdes interfaces at chip ports. with these modes the serdes logic and i/o can be tested one channel at a time in either the receive or transmit modes. the serdes characterization mode is available for only one quad (quad b) of the ort82g5. the characterization test mode is con?ured by setting bits in the control registers via the system bus. there are four bits that set up the test mode. the transmit characterization test mode is entered when schar_ena=1 and schar_txsel=1. entering this mode will cause chip port inputs to directly control the serdes low-speed trans- mit ports of one of the channels as shown in table 23. table 23. serdes transmit characterization mode the x in the table will be a single channel in serdes quad b, selected by the schar_chan control bits. the decoding of schar_chan is shown in table 24. chip port serdes input pschar_ckio0 tbcbx pschar_ldio[9:0] ldinbx[9:0] demux mux embedded core fpga logic 40 mrwdxx[39:0] 32 4 4 receive transmit twdxx[31:0] tcommaxx[3:0] tbit9xx[3:0] data checking data generation n m { parallel loopback connection test equipment lattice semiconductor orca ORT42G5 and ort82g5 data sheet 56 table 24. decoding of schar_chan the receive characterization test mode is entered when schar_ena=1 and schar_txsel=0, in this mode, one of the channels of serdes outputs is observed at chip ports as shown in table 25. the channel that is observed is also based on the decoding of schar_chan as shown in table 25. table 25. serdes receive characterization mode embedded core block ram there are two independent memory blocks (labeled a and b) built-into the embedded asic core (eac). each memory block has a capacity of 4k words by 36 bits. these two memory blocks (also called ?lices? are in addition to the block rams found in the fpga portion of the ort82g5. although the memory blocks/slices are in the eac part of the chip, they do not interact with the rest of the eac cir- cuits, but are standalone memories designed speci?ally to increase ram capacity in the ort82g5 chip. they can be used by logic implemented in the fpga portion of the fpsc. figure 34 represents one of the two available memory slices built into the eac. the index ? refers to the memory slice (x=a for slice a, x=b for slice b). each memory slice is organized into two sections, which are also labeled as a and b. in figure 34, sdram a is one sec- tion of slice x, and sdram b is another section of slice x. data can be written to both sections of a slice indepen- dently. however, a read access can access only one of sections a or b at any given time (csr_x=0 selects section a, csr_x=1 selects section b). the 36 bits written to or read from the memory slice are composed of 32 bits of data (bits 31:24, 23:16, 15:8, 7:0), and 4 bits of parity (bits 35,34,33,32). the core performs no parity checking functions. the data read from the memory is registered so that it works as a pipelined synchronous memory block. for illustration purposes, assuming that the memory slice in figure 34 is slice a (x=a), then certain signals apply to both sections of slice a. these include d_a[35:0], ckw_a, aw_a[10:0], bytewn_a[3:0], q_a[35:0], ckr_a, csr_a, and ar_a[10:0]. the bytewn_a[3:0] are byte and parity write enable bits for each byte and parity bit of data being written. bytewn_a[3] is associated with d_a[35,31:24]. bytewn_a[2] is associated with d_a[34,23:16]. bytewn_a[1] is associated with d_a[33,15:8]. bytewn_a[0] is associated with d_a[32,7:0]. the signals that are unique to each section of slice a are: cswa_a --enables writing to section a of slice a cswb_a -- enables writing to section b of slice a schar_chan0 schar_chan1 channel 0 0 ba 1 0 bb 0 1 bc 1 1 bd serdes output chip port bytsyncbx pschar_bytsync wdsyncbx pschar_wdsync cvobx pschar_cv ldoutbx[9:0] pschar_ldio[9:0] rbc0bx pschar_ckio0 rbc1bx pschar_ckio1 lattice semiconductor orca ORT42G5 and ort82g5 data sheet 57 as mentioned earlier, both sections of a slice can be written independently / simultaneously, due to the indepen- dent csw per section. the same signal illustration above applies to slice b by changing _a to _b. sdram a and sdram b in figure 34 refer to the built-in sections a and b of one eac ram slice. these sdrams should not be confused with the fpga sdrams, which are generated through module generator in isplever. the eac sdrams are always built-in to the embedded core section of the ort82g5/42g5 and their pins are accessed through the eac interface. in order for these pins to be available at the interface in the gener- ated hdl models from isplever, the ?se the extra memory in fpsc core checkbox needs to be checked in the customization window (after hitting the "customize" button) in module generator, while generating the ort82g5/42g5 core hdl. these signals will not otherwise show in the interface model. figure 35 and figure 36 show, per slice, timing diagrams for both write and read accesses. these ?ures do not include the _x section, which refers to either slice a or b, even though this is implied. signal names and functions are summarized in table 26 and follow the general orca series 4 naming conventions. figure 34. block diagram, embedded core memory slice 4k x 36 d_x[35:0] memory slice (1 of 2) 2k x 36 memory 2k x 36 memory (sram a) (sram b) write ports ckw_x cswa_x cswb_x aw_x[10:0] bytewn_x[3] bw[35,31:24] bytewn_x[2] bw[34,23:16] bytewn_x[1] bw[33,15:8] bytewn_x[0] bw[32,7:0] q_x[35:0] ckr_x csr_x ar_x[10:0] read ports side a / write selects side b fpga logic ram block read selects 36 11 36 11 note: x=[a,b] slice identifier parity data lattice semiconductor orca ORT42G5 and ort82g5 data sheet 58 figure 35. minimum timing specs for memory blocks-write cycle (-1 speed grade) figure 36. minimum timing specs for memory blocks-read cycle (-1 speed grade) in table 26, an input refers to a signal ?wing into the embedded core and an output refers to a signal ?wing out of the embedded core. csw[a,b] aw[10:0] ckw d[35:0] bytewn[3:0] 1.5 ns 2.0 ns 0.5 ns 0.3 ns 0.5 ns 0.3 ns 0.5 ns 0.3 ns 0.7 ns 0.3 ns ckr ar[10:0], csr q[35:0] 1.5 ns 1.5 ns 4.5 ns 0.5 ns 2.0 ns 0 ns lattice semiconductor orca ORT42G5 and ort82g5 data sheet 59 table 26. embedded memory slice core/fpga interface signal description memory maps de?ition of register types the serdes blocks within the ORT42G5 and ort82g5 cores have a set of status and control registers for ser- des operation. there is also other group of status and control registers which are implemented outside the ser- des, which are related to the serdes and other functional blocks in the fpsc core. (addresses for the control and status registers for the fpga portion of the device are detailed in the orca series 4 fpgas data sheet, which also describes the functions of those registers). ORT42G5 memory map each ORT42G5 serdes block has two independent channels. each channel is identi?d by both a quad identi- ?r, a or b, and a channel identi?r, c or d. (this naming convention follows that of the ort82g5.) the registers in ORT42G5 are 8-bit memory locations, which can be classi?d into status register and control register. status register read-only register to convey the status information of various operations within the fpsc core. an example is the state of the xaui link-state-machine. control register read-write register to set up the control inputs that de?e the operation of the fpsc core. reserved addresses for the fpsc register blocks are shown in table 29. table 27. structural register elements table 28 details the memory map for the fpsc portion of the ORT42G5 device. in both table 29 and table 28, the addresses are given as 18-bit hexadecimal (18?) values. the address may be sourced either through the micro- processor interface or a user master interface. the microprocessor interface (mpi) address bus is a 32-bit bus fpga/embedded core interface signal name] input (i) to or output (o) from core signal description memory slice interface signals d_[a:b][35:0] i data in?emory slice [a:b] ckw_[a:b] i write clock?emory slice [a:b]. cswa_[a:b] i write chip select for sram a?emory slice [a:b]. cswb_[a:b] i write chip select for sram b?emory slice [a:b]. aw_[a:b][10:0] i write address?emory slice [a:b]. bytewn_[a:b][3:0] i write control pins for byte-at-a-time write-memory slice [a:b]. q_[a:b][35:0] o data out?emory slice [a:b]. ckr_[a:b] i read clock?emory slice [a:b]. csr_[a:b] i read chip select?emory slice [a:b]. csr_[a:b]= 0 selects sram a. csr_[a:b]= 1 selects sram b. ar_[a:b][10:0] i read address?emory slice [a:b]. address (0x) description 300xx serdes a, internal registers. 301xx serdes b, internal registers. 308xx channel a [c or d] registers (external to serdes blocks). 309xx channel b [c or d] registers (external to serdes blocks). 30a0x global registers (external to serdes blocks). lattice semiconductor orca ORT42G5 and ort82g5 data sheet 60 which follows the power pc convention where address bit 0 is the msb and address bit 31 is the lsb. the mpi maps bits mpi_addr[14:31] to bits [17:0] of the system address bus. the user master interface (umi) has an 18- bit address bus and uses the opposite notation, where address line 17 is the msb and address line 0 is the lsb. the umi maps bits um_addr[17:0] to bits [17:0] of the system address bus. because of the address mapping done by the mpi and umi, the same hexadecimal address value is valid for both interfaces. the umi, internal and microprocessor interface data buses have both 32-bit data and 4-bit parity ?lds and the data ?lds are mapped 1:1 to each other, i.e., bit 0 is bit 0 for all three buses. the bit ordering is speci? to the tar- geted functional block. in the memory map, only bits [0:7] are speci?d and the convention followed for sub-?ld descriptions is to map the bits in the description directly to the bit order given in the bit column. for example, to select channel c as the source for the transmit and receive clocks, the register at location 30a00 should have bits 0, 2, 4 and 6 set to zero and bits 1, 3, 5 and 7 set to one. in the example in the previous paragraph, the bits being set are control bits and are independent of the msb/lsb convention used. the resulting bit pattern 01010101 maps to the hexadecimal value aa if the left-most bit is con- sidered the lsb and to 55 if the right-most bit is considered the lsb. in some cases, however, the data represents the value of a speci? parameter, such as a size or threshold level, and the value may be stored at more than one address location, since each location can hold only 8 bits of data. for a given register, either the msb or the lsb bit position is speci?d explicitly in the memory map. if the parameter value extends over multiple register locations, the relative bit or byte ordering is also speci?d. for additional information on the mpi and the system bus, see technical note tn1017, orca series 4 mpi/system bus. table 28. ORT42G5 memory map (0x) absolute address bit name reset value (0x) description serdes alarm registers (read only, clear on read), xx = [ac, ad, bc or bd] 30020 - ac 30030 - ad 30120 - bc 30130 - bd [0] reserved 00 reserved [1] lki_xx receive pll lock indication, channel xx. lki_xx = 1 indicates the receive pll is locked. [2] not used reserved [3] not used reserved [4:7] not used not used serdes alarm mask registers (read/write), xx = [ac, ad, bc or bd] 30021 - ac 30031 - ad 30121 - bc 30131 - bd [0] reserved ff reserved, must be set to 1. set to 1 on device reset. [1] mlki_xx mask receive pll lock indication, channel xx. [2] reserved reserved. must be set to 1. set to 1 on device reset. [3] reserved reserved. must be set to 1. set to 1 on device reset. [4] reserved reserved. must be set to 1. set to 1 on device reset. [5] reserved reserved. must be set to 1. set to 1 on device reset. [6] reserved reserved. must be set to 1. set to 1 on device reset. [7] reserved reserved. must be set to 1. set to 1 on device reset. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 61 serdes common transmit and receive channel con?uration registers (read/write), xx = [ac, ad, bc or bd] 30022 - ac 30032 - ad 30122 - bc 30132 - bd [0] txhr_xx 00 transmit half rate selection bit, channel xx. when txhr_xx = 1, hdout_xx's baud rate = (refclk[a:b]*10) and tck78[a:b] =(ref- clk[a:b]/4); when txhr_xx=0, hdout_xx's baud rate = (ref- clk[a:b]*20) and tck78[a:b]=(refclk[a:b]/2). txhr_xx = 0 on device reset. [1] pwrdnt_xx transmit powerdown control bit, channel xx. when pwrdnt_xx = 1, sections of the transmit hardware are powered down to conserve power. pwrdnt_xx = 0 on device reset. [2] pe0_xx transmit preemphasis selection bit 0, channel xx. pe0_xx and pe1_xx select one of three preemphasis settings for the transmit section. peo_xx=pe1_xx = 0, preemphasis is 0% peo_xx=1, pe1_xx = 0 or peo_xx=0, pe1_xx = 1, preemphasis is 12.5% peo_xx=pe1_xx = 1, preemphasis is 25%. peo_xx=pe1_xx = 0 on device reset. [3] pe1_xx [4] hamp_xx transmit half amplitude selection bit, channel xx. when hamp_xx = 1, the transmit output buffer voltage swing is limited to half its normal ampli- tude. otherwise, the transmit output buffer maintains its full voltage swing. hamp_xx = 0 on device reset. [5] reserved reserved. must be set to 0. set to 0 on device reset. [6] reserved reserved [7] 8b10bt_xx transmit 8b/10b encoder enable bit, channel xx. when 8b10bt_xx = 1, the 8b/10b encoder in the transmit path is enabled. otherwise, the data is passed unencoded. 8b10bt_xx = 0 on device reset. 30023 - ac 30033 - ad 30123 - bc 30133 - bd [0] rxhr_xx 20 receive half rate selection bit, channel xx. when rxhr_xx =1, hdin_xx's baud rate = (refclk[a:b]*10) and rck78[a:b]=(ref- clk[a:b]/4); when rxhr_xx=0, hdin_xx's baud rate = (ref- clk[a:b]*20) and rck78[a:b]=(refclk/2). rxhr_xx = 0 on device reset. [1] pwrdnr_xx receiver power down control bit, channel xx. when pwrdnr_xx = 1, sections of the receive hardware are powered down to conserve power. pwrdnr_xx = 0 on device reset. [2] reserved reserved. set to 1 on device reset. [3] 8b10br_xx receive 8b/10b decoder enable bit, channel xx. when 8b10br = 1, the 8b/10b decoder in the receive path is enabled. otherwise, the data is passed undecoded. 8b10br_xx = 0 on device reset. [4] linksm_xx link state machine enable bit, channel xx. when linksm_xx = 1, the receiver fiber channel link state machine is enabled. otherwise, the fibre channel link state machine is disabled. note: linksm_xx is ignored when xaui_mode_xx=1. linksm_xx = 0 on device reset. [5:7] not used not used. table 28. ORT42G5 memory map (continued) (0x) absolute address bit name reset value (0x) description lattice semiconductor orca ORT42G5 and ort82g5 data sheet 62 serdes common transmit and receive channel con?uration registers (read/write), xx = [ac, ad, bc or bd] 30024 - ac 30034 - ad 30124 - bc 30134 - bd [0] reserved see bit desc. reserved, must be 0. set to 0 on device reset. [1] mask_xx transmit and receive alarm mask bit, channel xx. when mask_xx = 1, the transmit and receive alarms of a channel are prevented from gener- ating an interrupt (i.e., they are masked or disabled). the mask_xx bit overrides the individual alarm mask bits in the alarm mask registers. mask_xx = 1 on device reset. [2] swrst_xx transmit and receive software reset bit, channel xx. when swrst_ss = 1, this bit provides the same function as the hardware reset, except that all con?uration register settings are unaltered. this is not a self-clearing bit. once set, this bit must be manually set and cleared. swrst = 0 on device reset. [3:6] not used not used [7] testen_xx transmit and receive test enable bit, channel xx. when testen_xx = 1, the transmit and receive sections are placed in test mode. the testmode_[a:b][4:0] bits in the global control registers specify the par- ticular test, and must also be set. note: when the global test enable bit gtesten_[a:b] = 0, the individual channel test enable bits are used to selectively place a channel in test or normal mode. when gtesten_[a:b] = 1, all channels in a block are set to test mode regardless of their testen setting. testen_xx = 0 on device reset. serdes global control registers (read write) - act on both channels in serdes block a or serdes block b. 30005 - a 30105 - b [0] reserved see bit desc. reserved, must be 0. set to 0 on device reset. [1] gmask_[a:b] global mask. when gmask_[a:b] = 1, the transmit and receive alarms of both channels in the serdes block are prevented from generating an interrupt (i.e., they are masked or disabled). the gmask_[a:b] bit over- rides the individual mask_xx bits. gmask_[a:b] = 1 on device reset. [2] gswrst_[a:b] software reset bit. the gswrst_[a:b] bit provides the same function as the hardware reset for the transmit and receive sections of both chan- nels, except that the device con?uration settings are not affected when gswrst_[a:b] is asserted. this is not a self-clearing bit. once set, this bit must be manually set and cleared. the gswrst_[a:b] bit overrides the individual swrst_xx bits. gswrst_[a:b] = 0 on device reset. [3] gpwrdnt_[a:b] powerdown transmit function. when gpwrdnt_[a:b] = 1, sections of the transmit hardware for both channels are powered down to conserve power. the gpwrdnt_[a:b] bit overrides the individual pwrdnt_xx bits. gpwrdnt_[a:b] = 0 on device reset. [4] gpwrdnr_[a:b] powerdown receive function. when gpwrdnr_[a:b] = 1, sections of the receive hardware for both channels are powered down to conserve power. the gpwrdnr_[a:b] bit overrides the individual pwrdnr_xx bits. gpwrdnr_[a:b] = 0 on device reset. [5] reserved reserved, 1 on device reset. [6] not used not used [7] gtesten_[a:b] test enable control. when gtesten_[a:b] = 1, the transmit and receive sections of both channels are placed in test mode. the gtesten_[a:b] bit overrides the individual testen_xx bits. gtesten_[a:b] = 0 on device reset. 30006 - a 30106 - b [0:4] testmode[a:b] 00 test mode - see test mode section for settings [5] not used not used [6:7] reserved reserved table 28. ORT42G5 memory map (continued) (0x) absolute address bit name reset value (0x) description lattice semiconductor orca ORT42G5 and ort82g5 data sheet 63 control registers (read/write), xx=[ac, ad, bc or bd] 30800 - ax 30900 - bx [0] 00 reserved for future use [1] reserved for future use [2] enbysync_xc enbysync_xc= 1 enables receiver byte synchronization for channel xc. enbysync_xc = 0 on device reset. [3] enbysync_xd enbysync_xd = 1 enables receiver byte synchronization for channel xa. enbysync_xd = 0 on device reset. [4] reserved for future use [5] reserved for future use [6] lckrefn_xc lckrefn_xc = 0 locks the receiver pll to reference clock for channel xc. lckrefn_xc =1 = locks the receiver to data for channel xx. note: when lckrefn_xx = 0, the corresponding lki_xx bit is also 0. lckrefn_xc = 0 on device reset. [7] lckrefn_xd lckrefn_xd = 0 locks the receiver pll to reference clock for channel xd. lckrefn_xd =1 = locks the receiver to data for channel xa. note: when lckrefn_xx = 0, the corresponding lki_xx bit is also 0. lckrefn_xd = 0 on device reset. 30801 - ax 30901 - bx [0] 00 reserved for future use [1] reserved for future use [2] loopenb_xc enable loopback mode for channel xc. when loopen_xc=1, the transmitter high-speed output is looped back to the receiver high-speed input. this mode is similar to high-speed loopback mode enabled by testmode_xx except that loopen_xx disables the high-speed serial output. loopen_xc=0 on device reset. [3] loopenb_xd enable loopback mode for channel xd. when loopen_xd=1, the transmitter high-speed output is looped back to the receiver high-speed input. this mode is similar to high-speed loopback mode enabled by testmode_xx except that loopen_xx disables the high-speed serial output. loopen_xd=0 on device reset. [4] reserved for future use [5] reserved for future use [6] nowdalign_xc word align disable bit. when nowdalign_xc=1, receiver word align- ment is disabled for channel xc. nowdalign_xc=0 on device reset. [7] nowdalign_xd word align disable bit. when nowdalign_xd=1, receiver word align- ment is disabled for channel xd. nowdalign_xd=0 on device reset. table 28. ORT42G5 memory map (continued) (0x) absolute address bit name reset value (0x) description lattice semiconductor orca ORT42G5 and ort82g5 data sheet 64 30810 - ax 30910 - bx [0]] 00 reserved for future use [1] reserved for future use [2] dowdalign_xc word realign bit. when dowdalign_xc transitions from 0 to 1, the receiver realigns on the next comma character for channel xc. nowdalign_xc=0 on device reset. [3] dowdalign_xc word realign bit. when dowdalign_xc transitions from 0 to 1, the receiver realigns on the next comma character for channel xc. nowdalign_xc=0 on device reset. [4] reserved for future use. set to zero. [5] reserved for future use. set to zero. [6] fmpu_str_en _xc enable multi-channel alignment for channel xc. when fmpu_str_en _xc = 0, channel xc is not part of a multi-chan- nel alignment group when fmpu_str_en _xc = 1, channel xc is part of a twin channel alignment (serdes block a or b) or quad channel alignment (both serdes blocks) group. [7] fmpu_str_en _xd enable multi-channel alignment for channel xd. when fmpu_str_en _xd = 0, channel xd is not part of a multi-chan- nel alignment group when fmpu_str_en _xd = 1, channel xd is part of a twin channel alignment (serdes block a or b) or quad channel alignment (both serdes blocks) group. 30811 - ax 30911 - bx [0:7] fmpu_synmode_ [a:b] 00 sync mode for block [a:b] 00000000 = no channel alignment 00001010 = twin channel alignment, serdes block [a:b] 00001111 = quad channel alignment (both serdes blocks) 30820 - ax 30920 - bx [0] 00 reserved for future use. [1] reserved for future use. [2] fmpu_resync1_xc resync a single channel. when fmpu_resync1_xc transitions from 0 to 1, the corresponding channel xc is resynchronized (the write and read pointers are reset). fmpu_str_en_xc=0 on device reset. [3] fmpu_resync1_xd resync a single channel. when fmpu_resync1_xd transitions from 0 to 1, the corresponding channel xd is resynchronized (the write and read pointers are reset). fmpu_str_en_xd=0 on device reset. [4] reserved for future use. [5] fmpu_resync2[a:b] resync a twin-channel group. when fmpu_resync2[a:b] transitions from a 0 to a 1, the corresponding twin-channel group is resynchronized. fmpu_resync2[a:b]=0 on device reset. [6] reserved for future use. [7] xaui_mode[a:b] controls use of xaui link state machine in place of fibre-channel state machine. when xaui_mode[a:b]=1, both channels in the serdes block enable their xaui link state machines. (linksm_xx bits are ignored). xaui_mode[a:b]=0 on device reset. 30821 - a 30921 - b [0] nochalgn [a:b] 00 bypass channel alignment. nochalgn [a:b] =1 causes bypassing of multi-channel alignment fifos for the corresponding serdes quad. nochalgn [a:b] =0 on device reset. [1:7] reserved for future use. table 28. ORT42G5 memory map (continued) (0x) absolute address bit name reset value (0x) description lattice semiconductor orca ORT42G5 and ort82g5 data sheet 65 30933 [0:3] 00 reserved for future use. [4:5] reserved for future use. [6] reserved for future use. [7] reserved for future use. status registers (read only, clear on read), xx = [ac, ad, bc or bd] 30804 - ax 30904 - bx [0:1] 00 reserved for future use. [2:3] reserved for future use. [4:5] xauistat_xc xaui status register. status of xaui link state machine for channel xc 00 ?no synchronization, 10 ?synchronization done, 11 ?not used, 01 ?no_comma (see xaui state machine) and at least one cv detected. xauistat_xc[0:1] = 00 on device reset. [6:7] xauistat_xd xaui status register. status of xaui link state machine for channel xd 00 ?no synchronization, 10 ?synchronization done, 11 ?not used, 01 ?no_comma (see xaui state machine) and at least one cv detected. xauistat_xd[0:1] = 00 on device reset. 30805 - ax 30905 - bx [0]] 00 reserved for future use. [1] reserved for future use. [2] demuxwas_xc status of word alignment. when demux_was_xc=1, word alignment is achieved for channel xc. demux_was_xc=0 on device reset. [3] demuxwas_xd status of word alignment. when demux_was_xd=1, word alignment is achieved for channel xd. demux_was_xd=0 on device reset. [4] reserved for future use. [5] reserved for future use. [6] ch24_sync_xc status of channel alignment. when ch24_sync_xc=1, multi-channel alignment is achieved for channel xc. ch24_sync_xc=0 on device reset. [7] ch24_sync_xd status of channel alignment. when ch24_sync_xd=1, multi-channel alignment is achieved for channel xd. ch24_sync_xd=0 on device reset. 30814 - a 30914 - b [0] 00 reserved for future use. [1] sync2_[a:b]_ovfl multi-channel over?w status. when sync2_[a:b]_ovfl=1, twin channel synchronization fifo over?w has occurred. sync2_[a:b]_ovfl=0 on device reset. [2:3] reserved for future use. [4] sync2_[a:b]_oos multi-channel out-of-sync status. when sync2_[a:b]_oos=1, twin channel synchronization has failed. sync2_[a:b]_oos=0 on device reset. [5:7] reserved for future use. table 28. ORT42G5 memory map (continued) (0x) absolute address bit name reset value (0x) description lattice semiconductor orca ORT42G5 and ort82g5 data sheet 66 common control registers (read/write) 30a00 [0:1] tcksela 00 transmit clock select. controls source of 78 mhz tck78 for serdes quad a 01 = channel ac 11 = channel ad [2:3] rcksela receive clock select. controls source of 78 mhz rck78 for serdes quad a 01 = channel ac 11 = channel ad [4:5] tckselb transmit clock select. controls source of 78 mhz tck78 for serdes quad b 01 = channel bc 11 = channel bd [6:7] rckselb receive clock select. controls source of 78 mhz rck78 for serdes quad b 01 = channel bc 11 = channel bd 30a01 [0:4] 00 reserved for future use [5:7] rx_fifo_min lsb s for the threshold for low address in rx_fifos. rx_fifo_min, bit 5 is lsb.* 30a02 [0:1] rx_fifo_min 00 msb s for the threshold for low address in rx_fifos. rx_fifo_min, bit 1 is msb.* [2] fmpu_resync4 resynchronize a four-channel group. when fpmpu_resync4 transi- tions from 0 to 1, the entire four-channel group is resynchronized. fmpu_resync4 = 0 on device reset [3:7] reserved for future use common status registers 30a03 [0] sync4_ovfl 00 read-only multi-channel over?w status. when sync4_ovfl=1, 4- channel synchronization fifo over?w has occurred. sync4_ovfl=0 on device reset. [1] sync4_oos read-only multi-channel out-of-sync status. when sync4_oos=1, 4-channel synchronization has failed. sync4_oos=0 on device reset. [2:7] reserved for future use. * useful values for rx_fifo_min [0:4] are 0 to 17(decimal) table 28. ORT42G5 memory map (continued) (0x) absolute address bit name reset value (0x) description lattice semiconductor orca ORT42G5 and ort82g5 data sheet 67 ort82g5 memory map each ort82g5 serdes block has eight independent channels. each channel is identi?d by both a quad identi- ?r, a or b, and a channel identi?r, a, b, c or d. the registers in ort82g5 are 8-bit memory locations, which can be classi?d into status register and control register. status register read-only register to convey the status information of various operations within the fpsc core. an example is the state of the xaui link-state-machine. control register read-write register to set up the control inputs that de?e the operation of the fpsc core. reserved addresses for the fpsc register blocks are shown in table 29. table 29. structural register elements table 30 details the memory map for the fpsc portion of the ort82g5 device. in both table 29 and table 30, the addresses are given as 18-bit hexadecimal (18?) values. the address may be sourced either through the micro- processor interface or a user master interface. the microprocessor interface (mpi) address bus is a 32-bit bus which follows the power pc convention where address bit 0 is the msb and address bit 31 is the lsb. the mpi maps bits mpi_addr[14:31] to bits [17:0] of the system address bus. the user master interface (umi) has an 18- bit address bus and uses the opposite notation, where address line 17 is the msb and address line 0 is the lsb. the umi maps bits um_addr[17:0] to bits [17:0] of the system address bus. because of the address mapping done by the mpi and umi, the same hexadecimal address value is valid for both interfaces. the umi, internal and microprocessor interface data buses have both 32-bit data and 4-bit parity ?lds and the data ?lds are mapped 1:1 to each other, i.e., bit 0 is bit 0 for all three buses. the bit ordering is speci? to the tar- geted functional block. in the memory map, only bits [0:7] are speci?d and the convention followed for sub-?ld descriptions is to map the bits in the description directly to the bit order given in the bit column. for example, to select channel c as the source for the transmit and receive clocks, the register at location 30a00 should have bits 0, 2, 4 and 6 set to zero and bits 1, 3, 5 and 7 set to one. in the example in the previous paragraph, the bits being set are control bits and are independent of the msb/lsb convention used. the resulting bit pattern 01010101 maps to the hexadecimal value aa if the left-most bit is con- sidered the lsb and to 55 if the right-most bit is considered the lsb. in some cases, however, the data represents the value of a speci? parameter, such as a size or threshold level, and the value may be stored at more than one address location, since each location can hold only 8 bits of data. for a given register, either the msb or the lsb bit position is speci?d explicitly in the memory map. if the parameter value extends over multiple register locations, the relative bit or byte ordering is also speci?d. for additional information on the mpi and the system bus, see technical note tn1017, orca series 4 mpi/system bus. address (0x) description 300xx serdes a, internal registers. 301xx serdes b, internal registers. 308xx channel a [a:d] registers (external to serdes blocks). 309xx channel b [a:d] registers (external to serdes blocks). 30a0x global registers (external to serdes blocks). lattice semiconductor orca ORT42G5 and ort82g5 data sheet 68 table 30. ort82g5 memory map (0x) absolute address bit name reset value (0x) description serdes alarm registers (read only), xx=[aa,...,bd] 30000 - aa 30010 - ab 30020 - ac 30030 - ad 30100 - ba 30110 - bb 30120 - bc 30130 - bd [0] reserved 00 reserved [1] lki_xx receive pll lock indication, channel xx. lki_xx = 1 indicates the receive pll is locked. [2] reserved reserved [3] reserved reserved [4:7] not used not used serdes alarm mask registers (read/write), xx=[aa,...,bd] 30001 - aa 30011 - ab 30021 - ac 30031 - ad 30101 - ba 30111 - bb 30121 - bc 30131 - bd [0] reserved ff reserved, must be set to 1. set to 1 on device reset. [1] mlki_xx mask receive pll lock indication, channel xx. [2] reserved reserved, must be set to 1. set to 1 on device reset. [3] reserved reserved, must be set to 1. set to 1 on device reset. [4] reserved reserved, must be set to 1. set to 1 on device reset. [5] reserved reserved, must be set to 1. set to 1 on device reset. [6] reserved reserved, must be set to 1. set to 1 on device reset. [7] reserved reserved, must be set to 1. set to 1 on device reset. serdes common transmit and receive channel con?uration registers (read/write), xx=[aa,...,bd] 30002 - aa 30012 - ab 30022 - ac 30032 - ad 30102 - ba 30112 - bb 30122 - bc 30132 - bd [0] txhr_xx 00 transmit half rate selection bit, channel xx. when txhr_xx = 1, hdout_xx's baud rate = (refclk[a:b]*10) and tck78[a:b] =(ref- clk[a:b]/4); when txhr_xx=0, hdout_xx's baud rate = (ref- clk[a:b]*20) and tck78[a:b]=(refclk[a:b]/2). txhr_xx = 0 on device reset. [1] pwrdnt_xx transmit powerdown control bit, channel xx. when pwrdnt_xx = 1, sections of the transmit hardware are powered down to conserve power. pwrdnt_xx = 0 on device reset. [2] pe0_xx transmit preemphasis selection bit 0, channel xx. pe0_xx and pe1_xx select one of three preemphasis settings for the transmit section. peo_xx=pe1_xx = 0, preemphasis is 0% peo_xx=1, pe1_xx = 0 or peo_xx=0, pe1_xx = 1, preemphasis is 12.5% peo_xx=pe1_xx = 1, preemphasis is 25%. peo_xx=pe1_xx = 0 on device reset. [3] pe1_xx [4] hamp_xx transmit half amplitude selection bit, channel xx. when hamp_xx = 1, the transmit output buffer voltage swing is limited to half its normal ampli- tude. otherwise, the transmit output buffer maintains its full voltage swing. hamp_xx = 0 on device reset. [5] reserved reserved. must be set to 0. set to 0 on device reset. [6] reserved reserved [7] 8b10bt_xx transmit 8b/10b encoder enable bit, channel xx. when 8b10bt_xx = 1, the 8b/10b encoder in the transmit path is enabled. otherwise, the data is passed unencoded. 8b10bt_xx = 0 on device reset. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 69 30003 - aa 30013 - ab 30023 - ac 30033 - ad 30103 - ba 30113 - bb 30123 - bc 30133 - bd [0] rxhr_xx 20 receive half rate selection bit, channel xx. when rxhr_xx =1, hdin_xx's baud rate = (refclk[a:b]*10) and rck78[a:b]=(ref- clk[a:b]/4); when rxhr_xx=0, hdin_xx's baud rate = (ref- clk[a:b]*20) and rck78[a:b]=(refclk/2). rxhr_xx = 0 on device reset. [1] pwrdnr_xx receiver power down control bit, channel xx. when pwrdnr_xx = 1, sections of the receive hardware are powered down to conserve power. pwrdnr_xx = 0 on device reset. [2] reserved reserved. set to 1 on device reset. [3] 8b10br_xx receive 8b/10b decoder enable bit, channel xx. when 8b10br = 1, the 8b/10b decoder in the receive path is enabled. otherwise, the data is passed undecoded. 8b10br_xx = 0 on device reset. [4] linksm_xx link state machine enable bit, channel xx. when linksm_xx = 1, the receiver fiber channel link state machine is enabled. otherwise, the fibre channel link state machine is disabled. note: linksm_xx is ignored when xaui_mode_xx=1. linksm_xx = 0 on device reset. [5:7] not used not used. serdes common transmit and receive channel con?uration registers (read/write), xx=[aa,...,bd] 30004 - aa 30014 - ab 30024 - ac 30034 - ad 30104 - ba 30114 - bb 30124 - bc 30134 - bd [0] reserved see bit descrip. reserved, must be set to 0. set to 0 on device reset. [1] mask_xx transmit and receive alarm mask bit, channel xx. when mask_xx = 1, the transmit and receive alarms of a channel are prevented from gener- ating an interrupt (i.e., they are masked or disabled). the mask_xx bit overrides the individual alarm mask bits in the alarm mask registers. mask_xx = 1 on device reset. [2] swrst_xx transmit and receive software reset bit, channel xx. when swrst_ss = 1, this bit provides the same function as the hardware reset, except that all con?uration register settings are unaltered. this is not a self-clearing bit. once set, this bit must be manually set and cleared. swrst = 0 on device reset. [3:6] not used not used. 0 on reset. [7] testen_xx transmit and receive test enable bit, channel xx. when testen_xx = 1, the transmit and receive sections are placed in test mode. the testmode_[a:b][4:0] bits in the global control registers specify the par- ticular test, and must also be set. note: when the global test enable bit gtesten_[a:b] = 0, the individual channel test enable bits are used to selectively place a channel in test or normal mode. when gtesten_[a:b] = 1, all channels are set to test mode regardless of their testen setting. testen_xx = 0 on device reset. table 30. ort82g5 memory map (continued) (0x) absolute address bit name reset value (0x) description lattice semiconductor orca ORT42G5 and ort82g5 data sheet 70 serdes global control registers (read write) act on all four channels in serdes quad a or serdes quad b. 30005 - a 30105 - b [0] reserved see bit descrip. reserved, must be set to 0. set to 0 on device reset. [1] gmask_[a:b] global mask. when gmask_[a:b] = 1, the transmit and receive alarms of all channels in the serdes quad are prevented from generating an interrupt (i.e., they are masked or disabled). the gmask_[a:b] bit over- rides the individual mask_xx bits. gmask_[a:b] = 1 on device reset. [2] gswrst_[a:b] software reset bit. the gswrst_[a:b] bit provides the same function as the hardware reset for the transmit and receive sections of all four channels, except that the device con?uration settings are not affected when gswrst_[a:b] is asserted. this is not a self-clearing bit. once set, this bit must be manually set and cleared. the gswrst_[a:b] bit overrides the individual swrst_xx bits. gswrst_[a:b] = 0 on device reset. [3] gpwrdnt_[a:b] powerdown transmit function. when gpwrdnt_[a:b] = 1, sections of the transmit hardware for all four channels of are powered down to con- serve power. the gpwrdnt_[a:b] bit overrides the individual pwrdnt_xx bits. gpwrdnt_[a:b] = 0 on device reset. [4] gpwrdnr_[a:b] powerdown receive function. when gpwrdnr_[a:b] = 1, sections of the receive hardware for all four channels are powered down to conserve power. the gpwrdnr_[a:b] bit overrides the individual pwrdnr_xx bits. gpwrdnr_[a:b] = 0 on device reset. [5] reserved reserved, 1 on device reset. [6] not used not used. 0 on reset. [7] gtesten_[a:b] test enable control. when gtesten_[a:b] = 1, the transmit and receive sections of all four channels are placed in test mode. the gtesten_[a:b] bit overrides the individual testen_xx bits. gtesten_[a:b] = 0 on device reset. 30006 - a 30106 - b [0:4] testmode[a:b] 00 testmode - see test mode section for settings [5] not used not used [6:7] reserved reserved control registers (read/write), xx=[aa,...,bd] 30800 - ax 30900 - bx [0]xa [1]xb [2]xc [3]xd enbysync_xx 00 enbysync_xx = 1 enables receiver byte synchronization for channel xx. enbysync_xx = 0 on device reset. [4]xa [5]xb [6]xc [7]xd lckrefn_xx lckrefn_xx = 0 locks the receiver pll to ref reference clock for channel xx. lckrefn_xx =1 = locks the receiver to data for channel xx. note: when lckrefn_xx = 0, the corresponding lki_xx bit is also 0. lckrefn_xx = 0 on device reset. 30801 - ax 30901 - bx [0]xa [1]xb [2]xc [3]xd loopenb_xx enable loopback mode for channel xx. when loopen_xx=1, the transmitter high-speed output is looped back to the receiver high-speed input. this mode is similar to high-speed loopback mode enabled by testmode_xx except that loopen_xx disables the high-speed serial output. loopen_xx=0 on device reset. [4]xa [5]xb [6]xc [7]xd nowdalign_xx word align disable bit. when nowdalign_xx=1, receiver word align- ment is disabled for channel xx. nowdalign_xx=0 on device reset. table 30. ort82g5 memory map (continued) (0x) absolute address bit name reset value (0x) description lattice semiconductor orca ORT42G5 and ort82g5 data sheet 71 30810 - ax 30910 - bx [0]xa [1]xb [2]xc [3]xd dowdalign_xx 00 word realign bit. when dowdalign_xx transitions from 0 to 1, the receiver realigns on the next comma character for channel xx. nowdalign_xx=0 on device reset. [4]xa [5]xb [6]xc [7]xd fmpu_str_en _xx enable multi-channel alignment for channel xx. when fmpu_str_en_xx=1, the corresponding channel participates in multi- channel alignment. fmpu_str_en_xx=0 on device reset. 30811 - ax 30911 - bx [0:1] xa [2:3] xb [4:5] xc [6:7] xd fmpu_synmod e_xx[0:1] 00 sync mode for xx 00 = no channel alignment 10 = twin channel alignment 01 = quad channel alignment 11 = eight channel alignment 30820 - ax 30920 - bx [0]xa [1]xb [2]xc [3]xd fmpu_resync1 _xx 00 resync a single channel. when fmpu_resync1_xx transitions from 0 to 1, the corresponding channel is resynchronized (the write and read pointers are reset). fmpu_str_en_xx=0 on device reset. [4] xa & xb [5] xc & xd fmpu_resync2 _x[1:2] resync a pair of channels. when fmpu_resync2_[a:b][1:2] transi- tions from a 0 to a 1, the corresponding channel pair is resynchronized. ffmpu_resync2_[a:b][1:2]=0 on device reset. [6] fmpu_resync4 [a:b] resync a four-channel group. when fmpu_resync4[a:b] transitions from a 0 to a 1, the corresponding four-channel group is resynchronized. fmpu_resync4[a:b]=0 on device reset. [7] xaui_mode[a:b] controls use of xaui link state machine in place of fibre-channel state machine. when xaui_mode[a:b]=1, all four channels in the serdes quad enable their xaui link state machines. (linksm_xx bits are ignored). xaui_mode[a:b]=0 on device reset. 30821 - a 30921 - b [0] nochalgn [a:b] 00 bypass channel alignment. nochalgn [a:b] =1 causes bypassing of multi-channel alignment fifos for the corresponding serdes quad. nochalgn [a:b] =0 on device reset. [1:7] reserved for future use. 30933 [0:3] reserved for future use. [4:5] schar_chan[0: 1] 00 select channel to test 00 = channel ba 10 = channel bb 01 =channel bc 11 = channel bd [6] schar_txsel 1=select tx option 0=select rx option [7] schar_ena 1=enable characterization of serdes b status registers (read only), xx=[aa,...,bd] 30804 - ax 30904 - bx [0:1] xa [2:3] xb [4:5] xc [6:7] xd xauistat_xx[0:1] 00 xaui status register. status of xaui link state machine for channel xx 00 ?no synchronization. 10 ?synchronization done. 11 ?not used. 01 ?no_comma (see xaui state machine) and at least one cv detected xauistat_xx[0:1] = 00 on device reset. table 30. ort82g5 memory map (continued) (0x) absolute address bit name reset value (0x) description lattice semiconductor orca ORT42G5 and ort82g5 data sheet 72 30805 - ax 30905 - bx [0]xa [1]xb [2]xc [3]xd demuxwas_xx 00 status of word alignment. when demux_was_xx=1, word alignment is achieved for channel xx. demux_was_xx=0 on device reset. [4]xa [5]xb [6]xc [7]xd ch248_sync_xx status of channel alignment. when ch248_sync_xx=1, multi-channel alignment is achieved for channel xx. ch248_sync_xx=0 on device reset. 30814 - ax 30914 - bx [0] xa & ab [1] xc & xd sync2_[a:b][1:2] ovfl 00 multi-channel over?w status. when sync2_[a:b][1:2]ovfl=1, dual- channel synchronization fifo over?w has occurred. sync2_[a:b][1:2]ovfl=0 on device reset. [2] sync4_ [a:b]ovfl multi-channel over?w status. when sync4_[a:b]ovfl=1, quad- channel synchronization fifo over?w has occurred. sync4_[a:b]ovfl=0 on device reset. [3] xa & ab [4] xc & xd sync2_[a:b][1:2] oos multi-channel out-of-sync status. when sync2_[a:b][1:2] oos=1, dual-channel synchronization has failed. sync2_[a:b][1:2] oos=0 on device reset. [5] sync4_[a:b]_oo s multi-channel out-of-sync status. when sync4_[a:b]_oos=1, quad- channel synchronization has failed. sync4_[a:b]_oos=0 on device reset. [6:7] reserved for future use. common control registers (read/write) 30a00 [0:1] tcksela 00 transmit clock select. controls source of 78 mhz tck78 for serdes quad a 00 = channel aa 10 = channel ab 01 = channel ac 11 = channel ad [2:3 rcksela receive clock select. controls source of 78 mhz rck78 for sedres quad a 00 = channel aa 10 = channel ab 01 = channel ac 11 = channel ad [4:5] tckselb transmit clock select. controls source of 78 mhz tck78 for serdes quad b 00 = channel ba 10 = channel bb 01 = channel bc 11 = channel bd [6:7] rckselb receive clock select. controls source of 78 mhz rck78 for serdes quad b 00 = channel ba 10 = channel bb 01 = channel bc 11 = channel bd 30a01 [0:4] 00 reserved for future use [5:7] rx_fifo_min lsb s for the threshold for low address in rx_fifos. rx_fifo_min, bit 5 is lsb. useful values for rx_fifo_min [0:4] are 0 to 17(decimal). table 30. ort82g5 memory map (continued) (0x) absolute address bit name reset value (0x) description lattice semiconductor orca ORT42G5 and ort82g5 data sheet 73 recommended board-level clocking for the ORT42G5 and ort82g5 option 1: asynchronous reference clocks between rx and tx devices each board that uses the ORT42G5 or ort82g5 as a transmit or receive device will have its own local reference clock as shown in figure 37. figure 37 shows the ort82g5 device on the switch card receiving data on two of its channels from a separate source. data tx1 is transmitted from a tx device with refclk1 as the reference clock and data tx2 is transmitted from a tx device with refclk2 as the reference clock. receive channel aa locks to the incom- ing data tx1 and receive channel ab locks to the incoming data tx2. the advantage of this clocking scheme is the fact that it is not necessary to distribute a reference clock (typically 156 mhz for 10ge and 155.52 mhz for oc-192 applications) across a backplane. figure 37. asynchronous clocking between rx and tx devices option 2: synchronous reference clocks to rx and tx devices in this type of clocking, a single reference clock is distributed to all receive and transmit devices in a system (figure 38). this distributed clocking scheme will permit maximum ?xibility in the usage of transmit and receive channels in the current silicon such as: all transmit and receive channels can be used within any quad in receive channel alignment or alignment bypass mode. in channel alignment mode, each receive channel operates on its own independent clock domain. 30a02 [0:1] rx_fifo_min 00 msb s for the threshold for low address in rx_fifos. rx_fifo_min, bit 1 is msb. useful values for rx_fifo_min [0:4] are 0 to 17(decimal). [2] fmpu_resync8 resynchronizes all 8 channels when it transitions from 0 to 1. status is a 0 on device reset. [3:7] reserved for future use. common status registers xx=[aa,...,bd] 30a03 [0] sync8_ovfl 00 read-only multi-channel over?w status. when sync8_ovfl=1, 8-channel synchronization fifo over?w has occurred. sync8_ovfl=0 on device reset. [1] sync8_oos read-only multi-channel out-of-sync status. when sync8_oos=1, 8-channel synchronization has failed. sync8_oos=0 on device reset. [2:7] reserved for future use. table 30. ort82g5 memory map (continued) (0x) absolute address bit name reset value (0x) description refclk 1 port card #1 port card #2 t x 1 t x 2 backplane ac ad switch card refclk 2 refclk 3 ORT42G5 or ort82g5 ORT42G5 or ort82g5 ORT42G5 or ort82g5 lattice semiconductor orca ORT42G5 and ort82g5 data sheet 74 the disadvantage with this scheme is the fact that it is dif?ult to distribute a 156 mhz reference clock across a backplane. this may require expensive clock driver chips on the board to drive clocks to different destinations within the speci?d jitter limits for the reference clock. figure 38. distributed reference clock to rx and tx devices refclk port card #1 port card #2 t x 1 t x 2 backplane ac ad switch card ORT42G5 or ort82g5 ORT42G5 or ort82g5 ORT42G5 or ort82g5 lattice semiconductor orca ORT42G5 and ort82g5 data sheet 75 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. the orca series 4 fpscs include circuitry designed to protect the chips from damaging substrate injection cur- rents and to prevent accumulations of static charge. nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress. recommended operating conditions serdes electrical and timing characteristics table 31. absolute maximum ratings parameter symbol min. max. unit storage temperature t stg ?65 150 ? power supply voltage with respect to ground v dd 33 ?0.3 4.2 v v dd io ?0.3 4.2 v v dd 15, v dd_ana, v ddgb 2.0 v input signal with respect to ground v in v ss ?0.3 v dd io + 0.3 v signal applied to high-impedance output v ss ?0.3 v dd io + 0.3 v maximum package body (soldering) temperature 220 ? parameter symbol min. max. unit power supply voltage with respect to ground 1 v dd33 3.0 3.6 v v dd15 1.425 1.575 v input voltages v in v ss ?0.3 v ddio + 0.3 v junction temperature t j ?40 125 ? serdes supply voltage v dd_ana, v ddgb 1.425 1.575 v serdes cml i/o supply voltage v ddib, v ddob 1.425 1.89 v 1. for fpga recommended operating conditions and electrical characteristics, see the recommended operating conditions and electr i- cal characteristics tables in the orca series 4 fpga data sheet (or4e04) and the orca series 4 i/o buffer technical note. fpsc standby currents (iddsb15 and iddsb33) are tested with the embedded core in the powered down state. parameter conditions max. 1 units ort82g5 power dissipation serdes, mux/demux, align fifo and i/o (per channel), 1.25 gbit/s 195 mw serdes, mux/demux, align fifo and i/o (per channel), 2.50 gbit/s 210 mw serdes, mux/demux, align fifo and i/o (per channel), 3.125 gbit/s 225 mw 8b/10b encoder/decoder (per channel) 50 mw ORT42G5 power dissipation serdes, mux/demux, align fifo and i/o (per channel), 1.25 gbit/s 265 mw serdes, mux/demux, align fifo and i/o (per channel), 2.50 gbit/s 275 mw serdes, mux/demux, align fifo and i/o (per channel), 3.125 gbit/s 295 mw 8b/10b encoder/decoder (per channel) 50 mw 1. with all channels operating, 1.575v supply. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 76 high speed data transmitter table 32 speci?s serial data output buffer parameters measured on devices with typical and worst case process parameters and over the full range of operation conditions. table 32. serial output timing and levels (cml i/o) transmitter output jitter is a critical parameter to systems with high speed data links. table 33 and table 34 specify the transmitter output jitter for typical and worst case devices over the full range of operating conditions. table 33. channel output jitter (3.125 gbps) table 34. channel output jitter (2.5 gbps) parameter min. typ. max. units rise time (20%?0%) 50 80 110 ps fall time (80%?0%) 50 80 110 ps common mode v dd ob - 0.30 v dd ob - 0.25 v dd ob - 0.15 v differential swing (full amplitude) 1 600 700 1000 mv p-p differential swing (half amplitude) 1 300 350 500 mv p-p output load (external) 86 1. differential swings measured at the end of 3 inches of fr-4 and 12 inches of coax cable. parameter device min. typ. 1 max. 1 units deterministic ORT42G5 0.12 0.21 ulp-p ort82g5 0.12 0.16 ulp-p random ORT42G5 0.05 0.10 ulp-p ort82g5 0.05 0.08 ulp-p total 2, 3 ORT42G5 0.17 0.31 ulp-p ort82g5 0.17 0.24 ulp-p 1. with prbs 2^7-1 data pattern, all channels operating, fpga logic active, refclk jitter of 30 ps., 0 o c to 85 o c, 1.425v to 1.575v supply. 2. wavecrest sia-3000 instrument used to measure one-sigma (rms) random jitter component value. this value is multiplied by 14 t o provide the peak-to-peak value that corresponds to a ber of 10 -12 . 3. total jitter measurement performed with wavecrest sia-3000 at a ber of 10 -12 . see instrument documentation and other wavecrest publi- cations for a detailed discussion of jitter types included in this measurement. parameter device min. typ. 1 max. 1 units deterministic ORT42G5 0.11 0.13 ulp-p ort82g5 0.11 0.13 ulp-p random ORT42G5 0.05 0.14 ulp-p ort82g5 0.05 0.07 ulp-p total 2, 3 ORT42G5 0.16 0.27 ulp-p ort82g5 0.16 0.20 ulp-p 1. with prbs 2^7-1 data pattern, all channels operating, fpga logic active, refclk jitter of 30 ps., 0 o c to 85 o c, 1.425v to 1.575v supply. 2. wavecrest sia-3000 instrument used to measure one-sigma (rms) random jitter component value. this value is multiplied by 14 t o provide the peak-to-peak value that corresponds to a ber of 10 -12 . 3. total jitter measurement performed with wavecrest sia-3000 at a ber of 10 -12 . see instrument documentation and other wavecrest publi- cations for a detailed discussion of jitter types included in this measurement. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 77 high speed data receiver table 35 speci?s receiver parameters measured on devices with worst case process parameters and over the full range of operation conditions. table 35. external data input speci?ations input data jitter tolerance a receiver?s ability to tolerate incoming signal jitter is very dependent on jitter type. high speed serial interface stan- dards have recognized the dependency on jitter type and have recently modified specifications to indicate toler- ance levels for different jitter types as they relate to specific protocols (e.g xaui, fc, infiniband etc.). sinusoidal jitter is considered to be a worst case jitter type. table 36 shows receiver specifications with 10 mhz sinusoidal jit- ter injection. xaui speci? jitter tolerance measurements were measured in a separate experiment detailed in tech- nical note tn1032, serdes test chip jitter, and are not re?cted in these results. table 36. receiver sinusoidal jitter tolerance speci?ations parameter conditions min. typ. max. units input data stream of nontransitions 8b/10b encode/decode off 72 bits sensitivity (differential), worst-case 1 3.125 gbps 80 mvp-p input levels 2 v ss - 0.3 v dd_ana + 0.3 v internal buffer resistance (each input to vddib) 40 50 60 pll lock time 3 note 2 1. with prbs 2^7-1 data pattern, all channels operating, fpga logic active, refclk jitter of 30 ps., t a = 0 o c to 85 o c, 1.425v to 1.575v sup- ply. 2. input level min + (input peak to peak swing)/2 common mode input voltage input level max - (input peak to peak swing)/2 3. the ORT42G5 and ort82g5 serdes receiver performs four levels of synchronization on the incoming serial data stream, providing ?st bit, then byte (character), then channel (32-bit word), and ?ally optional multi-channel alignment as described in tn1025. the pll lock time is the time required for the cdr pll to lock to the transitions in the incoming high-speed serial data stream. if the pll is unable to lock to the serial data stream, it instead locks to refclk to stabilize the voltage-controlled oscillator (vco), and periodical ly switches back to the serial data stream to again attempt synchronization. parameter conditions max. unit input data jitter tolerance @3.125gbps, typical 600 mv diff eye 1 0.75 u ip-p jitter tolerance @3.125gbps, worst case 600 mv diff eye 1 0.65 u ip-p jitter tolerance @2.5gbps,typical 600 mv diff eye 1 0.79 u ip-p jitter tolerance @2.5gbps, worst case 600 mv diff eye 1 0.67 u ip-p 1. with prbs 2^7-1 data pattern, all channels operating, fpga logic active, refclk jitter of 30 ps., t a = 0 o c to 85 o c, 1.425v to 1.575v supply. jitter measured with a wavecrest sia-3000. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 78 input eye-mask characterization figure 39. provides an eye-mask characterization of the serdes receiver input. the eye-mask is speci?d below for two different eye-mask heights. it provides guidance on a number of input parameters, including signal ampli- tude and rise time limits, noise and jitter limits, and p and n input skew tolerance. almost all detrimental character- istics of transmit signal and the interconnection link design result in eye-closure. this, combined with the eye- opening limitations of the line receiver, can provide a good indication of a link s ability to transfer data error-free. the clock and data recovery (cdr) portion of the ORT42G5 and ort82g5 serdes receiver has the ability to ?ter incoming signal jitter that is below the clock recovery pll bandwidth (about 3 mhz). the eye-mask speci?a- tions of table 37 are for jitter frequencies above the pll bandwidth of the cdr, which is a worst case condition. when jitter occurs at frequencies below the pll bandwidth, the receiver jitter tolerance is signi?antly better. for this case error-free data detection can occur even with a completely closed eye-mask. figure 39. receive data eye-diagram template (differential) table 37. receiver eye-mask speci?ations 1 parameter conditions value unit input data eye opening width (h)@ 3.125gbps v=175 mv diff 1 0.55 u ip-p eye opening width (t)@ 3.125gbps v=175 mv diff 1 0.15 u ip-p eye opening width (h)@ 3.125gbps v=600 mv diff 1 0.35 u ip-p eye opening width (t)@ 3.125gbps v=600 mv diff 1 0.10 u ip-p eye opening width (h)@ 2.5gbps v=175 mv diff 1 0.42 u ip-p eye opening width (t)@ 2.5gbps v=175 mv diff 1 0.15 u ip-p eye opening width (h)@ 2.5gbps v=600 mv diff 1 0.33 u ip-p eye opening width (t)@ 2.5gbps v=600 mv diff 1 0.10 u ip-p 1. with prbs 2^7-1 data pattern, 10 mhz sinusoidal jitter, all channels operating, fpga logic active, refclk jitter of 30 ps., t a = 0 o c to 85 o c, 1.425v to 1.575v supply. h v 1.2v ui t lattice semiconductor orca ORT42G5 and ort82g5 data sheet 79 external reference clock the external reference clock selection and its interface are a critical part of system applications for this product. table 38 speci?s reference clock requirements, over the full range of operating conditions. the designer is encourage to read tn1040, serdes reference clock, which discusses various aspects of this system element and its interconnection. table 38. reference clock speci?ations (refclkp and refclkn) embedded core timing characteristics table 39 summarizes the end-to-end latencies through the embedded core for the various modes. all latencies are given in clock cycles for system clocks at half the refclk_[a:b] frequency. for a refclk_[a:b] of 156.25 mhz, a system clock cycle is 6.4 ns. table 39. signal latencies, embedded core parameter min. typ. max. units frequency range 60 185 mhz frequency tolerance 1 -350 350 ppm duty cycle (measured at 50% amplitude point) 40 50 60 % rise time 500 1000 ps fall time 500 1000 ps p? input skew 75 ps differential amplitude 500 800 2 x v ddib mv p-p common mode level v single-ended/2 0.75 v dd 15 ?(v single-ended/2 ) v single-ended amplitude 250 400 v ddib mv p-p input capacitance (at refclkp) 5 pf input capacitance (at refclkn) 5 pf 1. this speci?ation indicates the capability of the high speed receiver cdr pll to acquire lock when the reference clock frequ ency and incoming data rate are not synchronized. operating mode signal latency (max.) transmit path 5 clock cycles receive path multi-channel alignment bypassed 1 4.5 clock cycles with multi-channel alignment 1 13.5-22.5 clock cycles 1. with multi-channel alignment, the latency is largest when the skew between channels is at the maximum that can be correctly compensated for (18 clock cycles). the latency speci?d in the table is for data from the channel received ?st. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 80 pin descriptions this section describes the pins found on the series 4 fpgas. any pin not described in this table is a user-program- mable i/o. during con?uration, the user-programmable i/os are 3-stated with an internal pull-up resistor. if any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor after con?uration. the pin descriptions in table and throughout this data sheet show active-low signals with an overscore. the pack- age pinout tables that follow, show this as a signal ending with _n. for example ldc and ldc_n are equivalent. table 40. pin descriptions symbol i/o description dedicated pins v dd 33 3.3v positive power supply. this power supply is used for 3.3v con?uration rams and internal plls. when using plls, this power supply should be well isolated from all other power supplies on the board for proper operation. v dd 15 1.5v positive power supply for internal logic. v dd io positive power supply used by i/o banks. v ss ground. ptemp i temperature sensing diode pin. dedicated input. reset i during con?uration, reset forces the restart of con?uration and a pull-up is enabled. after con?uration, reset can be used as a general fpga input or as a direct input, which causes all plc latches/ffs to be asynchronously set/reset. cclk o in the master and asynchronous peripheral modes, cclk is an output which strobes con?ura- tion data in. i in the slave or readback after con?uration, cclk is input synchronous with the data on din or d[7:0]. cclk is an output for daisy-chain operation when the lead device is in master, periph- eral, or system bus modes. done i as an input, a low level on done delays fpga start-up after con?uration. 1 o as an active-high, open-drain output, a high level on this signal indicates that con?uration is complete. done has an optional pull-up resistor. prgrm i prgrm is an active-low input that forces the restart of con?uration and resets the boundary- scan circuitry. this pin always has an active pull-up. rd_cfg i this pin must be held high during device initialization until the init pin goes high. this pin always has an active pull-up. during con?uration, rd_cfg is an active-low input that activates the ts_all function and 3-states all of the i/o. after con?uration , rd_cfg can be selected (via a bit stream option) to activate the ts_all function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on rd_cfg will initiate readback of the con?uration data, including pfu output states, starting with frame address 0. rd_data/tdo o rd_data/tdo is a dual-function pin. if used for readback, rd_data provides con?uration data out. if used in boundary-scan, tdo is test data out. cfg_irq /mpi_irq o during jtag, slave, master, and asynchronous peripheral con?uration assertion on this cfg_irq (active-low) indicates an error or errors for block ram or fpsc initialization. mpi active-low interrupt request output, when the mpi is used. lvds_r reference resistor connection for controlled impedance termination of series 4 fpga lvds inputs. special-purpose pins m[3:0] i during powerup and initialization, m0?3 are used to select the con?uration mode with their values latched on the rising edge of init . during con?uration, a pull-up is enabled. i/o after con?uration, these pins are user-programmable i/o. 1 pll_ck[0:7][tc] i semi-dedicated pll clock pins. during con?uration they are 3-stated with a pull up. i/o these pins are user-programmable i/o pins if not used by plls after con?uration. p[tblr]clk[1:0][tc] i pins dedicated for the primary clock. input pins on the middle of each side with differential pair- ing. i/o after con?uration these pins are user programmable i/o, if not used for clock inputs. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 81 tdi, tck, tms i if boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. if boundary-scan is not selected, all boundary-scan functions are inhibited once con?uration is complete. even if boundary-scan is not used, either tck or tms must be held at logic 1 during con?uration. each pin has a pull-up enabled during con?uration. i/o after con?uration, these pins are user-programmable i/o if boundary scan is not used. 1 rdy/b usy /rclk o during con?uration in asynchronous peripheral mode, rdy/rclk indicates another byte can be written to the fpga. if a read operation is done when the device is selected, the same sta- tus is also available on d7 in asynchronous peripheral mode. during the master parallel con?uration mode, rclk is a read output signal to an external memory. this output is not normally used. i/o after con?uration this pin is a user-programmable i/o pin. 1 hdc o high during con?uration is output high until con?uration is complete. it is used as a control output, indicating that con?uration is not complete. i/o after con?uration, this pin is a user-programmable i/o pin. 1 ldc o lo w dur ing con gur ation is output low until con?uration is complete. it is used as a control out- put, indicating that con?uration is not complete. i/o after con?uration, this pin is a user-programmable i/o pin. 1 init i/o init is a bidirectional signal before and during con?uration. during con?uration, a pull-up is enabled, but an external pull-up resistor is recommended. as an active-low open-drain output, init is held low during power stabilization and internal clearing of memory. as an active-low input, init holds the fpga in the wait-state before the start of con?uration. after con?uration, this pin is a user-programmable i/o pin. 1 cs0 , cs1 i cs0 and cs1 are used in the asynchronous peripheral, slave parallel, and microprocessor con- ?uration modes. the fpga is selected when cs0 is low and cs1 is high. during con?ura- tion, a pull-up is enabled. i/o after con?uration, if mpi is not used, these pins are user-programmable i/o pins. 1 rd /mpi_strb i rd is used in the asynchronous peripheral con?uration mode. a low on rd changes d[7:3] into a status output. wr and rd should not be used simultaneously. if they are, the write strobe overrides. this pin is also used as the mpi data transfer strobe. as a status indication, a high indicates ready, and a low indicates busy. wr /mpi_rw i wr is used in asynchronous peripheral mode. a low on wr transfers data on d[7:0] to the fpga. in mpi mode, a high on mpi_rw allows a read from the data bus, while a low causes a write transfer to the fpga. i/o after con?uration, if the mpi is not used, wr /mpi_rw is a user-programmable i/o pin. 1 ppc_a[14:31] i during mpi mode the ppc_a[14:31] are used as the address bus driven by the powerpc bus master utilizing the least-signi?ant bits of the powerpc 32-bit address. mpi_burst i mpi_b urst is driven low to indicate a burst transfer is in progress in mpi mode. driven high indicates that the current transfer is not a burst. mpi_bdip i mpi_bdip is driven by the powerpc processor in mpi mode. assertion of this pin indicates that the second beat in front of the current one is requested by the master. negated before the burst transfer ends to abort the burst data phase. mpi_tsz[0:1] i mpi_tsz[0:1] signals are driven by the bus master in mpi mode to indicate the data transfer size for the transaction. set 01 for byte, 10 for half-word, and 00 for word. a[21:0] o during master parallel mode a[21:0] address the con?uration eproms up to 4m bytes. i/o if not used for mpi these pins are user-programmable i/o pins after con?uration. 1 mpi_ack o in mpi mode this is driven low indicating the mpi received the data on the write cycle or returned data on a read cycle. i/o if not used for mpi these pins are user-programmable i/o pins after con?uration. 1 table 40. pin descriptions (continued) symbol i/o description lattice semiconductor orca ORT42G5 and ort82g5 data sheet 82 mpi_clk i this is the powerpc synchronous, positive-edge bus clock used for the mpi interface. it can be a source of the clock for the embedded system bus. if mpi is used this will be the amba bus clock. i/o if not used for mpi these pins are user-programmable i/o pins after con?uration. 1 mpi_tea o a low on the mpi transfer error acknowledge indicates that the mpi detects a bus error on the internal system bus for the current transaction. i/o if not used for mpi these pins are user-programmable i/o pins after con?uration. 1 mpi_rtry o this pin requests the mpc860 to relinquish the bus and retry the cycle. i/o if not used for mpi these pins are user-programmable i/o pins after con?uration. 1 d[0:31] i/o selectable data bu s width from 8, 16, 32-bit in mpi mode. driven by the bus master in a write transaction and driven by mpi in a read transaction. i d[7:0] receive con?uration data during master parallel, peripheral, and slave parallel con?u- ration modes when wr is low and each pin has a pull-up enabled. during serial con?uration modes, d0 is the din input. o d[7:3] output internal status for asynchronous peripheral mode when rd is low. i/o after con?uration, if mpi is not used, the pins are user-programmable i/o pins. 1 dp[0:3] i/o selectable parity bus width in mpi mode from 1, 2, 4-bit, dp[0] for d[0:7], dp[1] for d[8:15], dp[2] for d[16:23], and dp[3] for d[24:31]. after con?uration, if mpi is not used, the pins are user-programmable i/o pin. 1 din i during slave serial or master serial con?uration modes, din accepts serial con?uration data synchronous with cclk. during parallel con?uration modes, din is the d0 input. during con- ?uration, a pull-up is enabled. i/o after con?uration, this pin is a user-programmable i/o pin. 1 dout o during con?uration, dout is the serial data output that can drive the din of daisy-chained slave devices. data out on dout changes on the rising edge of cclk. i/o after con?uration, dout is a user-programmable i/o pin. 1 testcfg (ort82g5 only) i during con?uration this pin should be held high, to allow con?uration to occur. a pull up is enabled during con?uration. i/o after con?uration, testcfg is a user programmable i/o pin. 1 1. the fpga states of operation section in the orca series 4 fpgas data sheet (ort82g5 only) contains more information on how to con- trol these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing o f the simulta- neous release of all other con?uration pins (and the activation of all user i/os) is controlled by a second set of options. table 40. pin descriptions (continued) symbol i/o description lattice semiconductor orca ORT42G5 and ort82g5 data sheet 83 this section describes device i/o signals to/from the embedded core. table 41. fpsc function pin descriptions symbol i/o description common signals for both serdes quad a and b pasb_resetn i active low reset for the embedded core. all non-serdes speci? registers (addresses 308***, 309***, 30a***) in the embedded core are not reset. 1 pasb_tristn i active low 3-state for embedded core output buffers. 1 pasb_pdn i active low power down of all serdes blocks and associated i/os. 1 pasb_testclk i clock input for bist and loopback test. 1 pbist_test_enn i selection of pasb_testclk input for bist test. 1 ploop_test_enn i selection of pasb_testclk input for loopback test. 1 pmp_testclk i clock input for microprocessor in test mode. 1 pmp_testclk_enn i selection of pmp_testclk in test mode. 1 psys_dobistn i input to start bist test. 1 psys_rssig_all o output result of bist test. serdes quad a and b pins refclkn_a i cml reference clock input?erdes quad a. refclkp_a i cml reference clock input?erdes quad a. refclkn_b i cml reference clock input?erdes quad b. refclkp_b i cml reference clock input?erdes quad b. rext_a reference resistor ?serdes quad a. rext_b reference resistor ?serdes quad b. rextn_a reference resistor ?serdes quad -. a 3.32 k w ?1% resistor must be connected across rext_b and rextn_b. this resistor should handle a current of 300 ?. rextn_b reference resistor ?serdes quad b. a 3.32 k ?1% resistor must be con- nected across rext_b and rextn_b. this register should handle a current of 300 ? hdinn_aa (ort82g5 only) i high-speed cml receive data input ?serdes quad a, channel a. hdinp_aa (ort82g5 only) i high-speed cml receive data input ?serdes quad a, channel a. hdinn_ab (ort82g5 only) i high-speed cml receive data input ?serdes quad a, channel b. hdinp_ab (ort82g5 only) i high-speed cml receive data input ?serdes quad a, channel b. hdinn_ac i high-speed cml receive data input ?serdes quad a, channel c. hdinp_ac i high-speed cml receive data input ?serdes quad a, channel c. hdinn_ad i high-speed cml receive data input ?serdes quad a, channel d. hdinp_ad i high-speed cml receive data input ?serdes quad a, channel d. hdinn_ba (ort82g5 only) i high-speed cml receive data input ?serdes quad b, channel a. hdinp_ba (ort82g5 only) i high-speed cml receive data input ?serdes quad b, channel a. hdinn_bb (ort82g5 only) i high-speed cml receive data input ?serdes quad b, channel b. hdinp_bb (ort82g5 only) i high-speed cml receive data input ?serdes quad b, channel b. hdinn_bc i high-speed cml receive data input ?serdes quad b, channel c. hdinp_bc i high-speed cml receive data input ?serdes quad b, channel c. hdinn_bd i high-speed cml receive data input ?serdes quad b, channel d. hdinp_bd i high-speed cml receive data input ?serdes quad b, channel d. serdes quad a and b pins hdoutn_aa (ort82g5 only) o high-speed cml transmit data output ?serdes quad a, channel a. hdoutp_aa (ort82g5 only) o high-speed cml transmit data output ?serdes quad a, channel a. hdoutn_ab (ort82g5 only) o high-speed cml transmit data output ?serdes quad a, channel b. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 84 hdoutp_ab (ort82g5 only) o high-speed cml transmit data output ?serdes quad a, channel b. hdoutn_ac o high-speed cml transmit data output ?serdes quad a, channel c. hdoutp_ac o high-speed cml transmit data output ?serdes quad a, channel c. hdoutn_ad o high-speed cml transmit data output ?serdes quad a, channel d. hdoutp_ad o high-speed cml transmit data output ?serdes quad a, channel d. hdoutn_ba (ort82g5 only) o high-speed cml transmit data output ?serdes quad b, channel a. hdoutp_ba (ort82g5 only) o high-speed cml transmit data output ?serdes quad b, channel a. hdoutn_bb (ort82g5 only) o high-speed cml transmit data output ?serdes quad b, channel b. hdoutp_bb (ort82g5 only) o high-speed cml transmit data output ?serdes quad b, channel b. hdoutn_bc o high-speed cml transmit data output ?serdes quad b, channel c. hdoutp_bc o high-speed cml transmit data output ?serdes quad b, channel c. hdoutn_bd o high-speed cml transmit data output ?serdes quad b, channel d. hdoutp_bd o high-speed cml transmit data output ?serdes quad b, channel d. power and ground v dd ib_aa (ort82g5 only) 1.8v/1.5v power supply for high-speed serial input buffers. v dd ib_ab (ort82g5 only) 1.8v/1.5v power supply for high-speed serial input buffers. v dd ib_ac 1.8v/1.5v power supply for high-speed serial input buffers. v dd ib_ad 1.8v/1.5v power supply for high-speed serial input buffers. v dd ib_ba (ort82g5 only) 1.8v/1.5v power supply for high-speed serial input buffers. v dd ib_bb (ort82g5 only) 1.8v/1.5v power supply for high-speed serial input buffers. v dd ib_bc 1.8v/1.5v power supply for high-speed serial input buffers. v dd ib_bd 1.8v/1.5v power supply for high-speed serial input buffers. v dd ob_aa (ort82g5 only) 1.8v/1.5v power supply for high-speed serial output buffers. v dd ob_ab (ort82g5 only) 1.8v/1.5v power supply for high-speed serial output buffers. v dd ob_ac 1.8v/1.5v power supply for high-speed serial output buffers. v dd ob_ad 1.8v/1.5v power supply for high-speed serial output buffers. v dd ob_ba (ort82g5 only) 1.8v/1.5v power supply for high-speed serial output buffers. v dd ob_bb (ort82g5 only) 1.8v/1.5v power supply for high-speed serial output buffers. v dd ob_bc 1.8v/1.5v power supply for high-speed serial output buffers. v dd ob_bd 1.8v/1.5v power supply for high-speed serial output buffers. v dd gb_a 1.5v guard band power supply. v dd gb_b 1.5v guard band power supply. v dd _ana 1.5v power supply for serdes analog receive and transmit circuitry. 1. should be externally connected on board to 3.3v pull-up resistor. table 41. fpsc function pin descriptions (continued) symbol i/o description lattice semiconductor orca ORT42G5 and ort82g5 data sheet 85 power supplies for ORT42G5 and ort82g5 power supply descriptions table shows the ORT42G5 and ort82g5 fpga and embedded core power supply groupings. vdd33 is a 3.3v positive power supply used for 3.3v con?uration rams and internal plls. when using plls, this power supply should be well isolated from all other power supplies on the board for proper operation. the ?e vddio supplies are positive power supply used by the fpga i/o banks.the 1.5 volt digital power supplies are used for the fpga and the embedded core transmit and receive digital logic including the microprocessor logic. the 1.5 volt analog power supply is used for high-speed analog circuitry in the embedded core between the i/o buffers and the digital logic. the rx input buffer power supplies are used to power the input (receive) buffers. the tx output buffer sup- plies are used to power the output (transmit) buffers. the rx and tx buffer power supplies can be independently set to 1.5v or 1.8v, depending on the end application. the guard band supplies are independent connection brought out to pins. table 42. power supplies recommended power supply connections ideally, a board should have the power supplies described below: vdd33 and vddio supplies for the fpga logic a single 1.5v source to supply power to fpga and core digital logic. a dedicated 1.5v power supply for the analog power pins. this will allow the end user to minimize noise. the guard band pins can also be sourced from the analog power supplies. tx output buffer power. the power supplies to the ts output buffers should be isolated from the rest of the board power supplies. special care must be taken to minimize noise when providing board level power to these output buffers. the power supply can be 1.5v or 1.8v depending on the end application. rx input buffer power. the power supplies to the rx input buffers should be isolated from the rest of the board power supplies. special care must be taken to minimize noise when providing board level power to these input buffers. the power supply can be 1.5v or 1.8v depending on the end application. recommended power supply filtering scheme the board connections of the various serdes v dd and v ss pins are critical to system performance. an example demonstration board schematic is available at www .latticesemi.com . power supply ?tering is in the form of: a parallel bypass capacitor network consisting of 10 ?, 0.1 ?, and 1.0 ? caps close to the power source. a parallel bypass capacitor network consisting of 0.01 ? and 0.1 ? close to the pin on the ORT42G5. fpga supplies fpga and core digital supply 1.5v analog 1.5v tx output buffers 1.5v/1.8v (v dd ob) rx input buffers 1.5v/1.8v (v dd ib) guard band 1.5v (v dd gb) vdd33 v dd 15 v dd _ana v dd ob_aa 1 v dd ib_aa 1 v dd gb_a vddio0 v dd ob_ab 1 v dd ib_ab 1 v dd gb_b vddio1 v dd ob_ac v dd ib_ac vddio5 v dd ob_ad v dd ib_ad vddio6 v dd ob_ba 1 v dd ib_ba 1 vddio7 v dd ob_bb 1 v dd ib_bb 1 v dd ob_bc v dd ib_bc v dd ob_bd v dd ib_bd 1. ort82g5 only. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 86 example connections are shown in figure 40. the naming convention for the power supply sources shown in the ?ure are as follows: supply_1.5v ?tx-rx digital, auxiliary power pins. supply_v dd ib ?input rx buffer power pins. supply_v dd ob ?output tx buffer power pins. supply_v dd ana ?tx analog power pins, rx analog power pins, guard band power pins. figure 40. power supply filtering 0.1 f 4.7 h 10 f v dd 15 supply_1.5 v source pin supply_v dd analog v dd ib supply_v dd ib v dd ob supply_v dd ob ? network for every 2 pins ? network for every 2 pins ? each for v dd gb_[a,b] ? network for every 2 pins ? network for every 2 pin s 1 f 0.01 f 0.1 f 0.1 f 10 f 1 f 0.01 f 0.1 f v dd _ana 0.1 f 10 f 1 f 0.01 f 0.1 f 0.1 f 10 f 1 f 0.01 f 0.1 f 4.7 h 4.7 h 4.7 h lattice semiconductor orca ORT42G5 and ort82g5 data sheet 87 package information package pinouts table 43 provides the number of user-programmable i/os available for each package. table 43. i/o summary table 44 and table 45 provide the package pin and pin function for the ORT42G5 and ort82g5 fpsc and pack- ages. the bond pad name is identi?d in the pio nomenclature used in the isplever system software design edi- tor. the bank column provides information as to which output voltage level bank the given pin is in. the group column provides information as to the group of pins the given pin is in. this is used to show which vref pin is used to provide the reference voltage for single-ended limited-swing i/os. if none of these buffer types (such as sstl, gtl, hstl) are used in a given group, then the vref pin is available as an i/o pin. when the number of fpga bond pads exceeds the number of package pins, bond pads are unused. when the number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects). when a package pin is to be left as a no connect for a speci? die, it is indicated as a note in the device column for the fpga. the tables provide no information on unused pads. as shown in the pair columns in table 38, differential pairs and physical locations are numbered within each bank (e.g., l19c-a0 is the nineteenth pair in an associated bank). a ? indicates complementary differential, whereas a ? indicates true differential. an _a0 indicates the physical location of adjacent balls in either the horizontal or ver- tical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates balls are diagonally adjacent, separated by one physical ball. v ref pins, shown in the pin description columns in table 44 and table 45, are associated to the bank and group (e.g., vref_tl_01 is the v ref for group one of the top left (tl) bank. device ORT42G5 ort82g5 user programmable i/o 204 372 available programmable differential pair pins 166 330 fpga con?uration pins 7 7 fpga dedicated function pins 2 2 core function pins 32 71 vdd15 49 63 vdd33 8 10 vddio 34 32 vss 112 91 vddgb 2 2 vddib 4 8 vddob 8 12 vdd_ana 22 8 no connect 0 2 total package pins 484 680 lattice semiconductor orca ORT42G5 and ort82g5 data sheet 88 table 44. ORT42G5 484-pin pbgam (fpbga) pinout 484-pbgam vddio bank vref group i/o pin description additional function 484-pbgam e4 - - o prd_data rd_data/tdo - c20 - - vdd15 vdd15 - - d3 - - i preset_n reset_n - f5 - - i prd_cfg_n rd_cfg_n - f4 - - i pprgrm_n prgrm_n - c2 0 (tl) 7 io pl2d pll_ck0c/hppll l1c c1 0 (tl) 7 io pl2c pll_ck0t/hppll l1t f3 0 (tl) 7 io pl3c vref_0_07 - a1 - - vss vss - - d2 0 (tl) 7 io pl4d d5 l2c d1 0 (tl) 7 io pl4c d6 l2t e7 0 (tl) - vddio0 vddio0 - - e2 0 (tl) 8 io pl5d hdc l3c e1 0 (tl) 8 io pl5c ldc_n l3t g3 0 (tl) 8 io pl5a - - g4 0 (tl) 9 io pl6c d7 - f2 0 (tl) 9 io pl7d vref_0_09 l4c f1 0 (tl) 9 io pl7c a17/ppc_a31 l4t g2 0 (tl) 9 io pl8d cs0_n l5c g1 0 (tl) 9 io pl8c cs1 l5t e8 0 (tl) - vddio0 vddio0 - - a2 - - vss vss - - h1 0 (tl) 10 io pl10d init_n l6c h2 0 (tl) 10 io pl10c dout l6t e5 - - vdd15 vdd15 - - h4 0 (tl) 10 io pl11d vref_0_10 - h3 0 (tl) 10 io pl11c a16/ppc_a30 - j1 7 (cl) 1 io pl12d a15/ppc_a29 l7c j2 7 (cl) 1 io pl12c a14/ppc_a28 l7t j4 7 (cl) 1 io pl13c d4 - g7 - - vss vss - - j3 7 (cl) 2 io pl14d rdy/busy_n/rclk - k6 7 (cl) - vddio7 vddio7 - - k1 7 (cl) 2 io pl15d a13/ppc_a27 l8c k2 7 (cl) 2 io pl15c a12/ppc_a26 l8t k3 7 (cl) 3 io pl16c - - k4 7 (cl) 3 io pl17d a11/ppc_a25 - g8 - - vss vss - - f8 - - vdd15 vdd15 - - k5 7 (cl) 4 io pl19d rd_n/mpi_strb_n - l1 7 (cl) 4 io pl20d plck0c l9c l2 7 (cl) 4 io pl20c plck0t l9t l6 7 (cl) - vddio7 vddio7 - - f9 - - vdd15 vdd15 - - lattice semiconductor orca ORT42G5 and ort82g5 data sheet 89 g9 - - vss vss - - l3 7 (cl) 5 io pl21d a10/ppc_a24 l10c l4 7 (cl) 5 io pl21c a9/ppc_a23 l10t l5 7 (cl) 5 io pl22d a8/ppc_a22 - f10 - - vdd15 vdd15 - - g10 - - vss vss - - m3 7 (cl) 6 io pl24d plck1c l11c m4 7 (cl) 6 io pl24c plck1t l11t n4 7 (cl) 6 io pl25c a7/ppc_a21 - m2 7 (cl) 6 io pl26d a6/ppc_a20 l12c m1 7 (cl) 6 io pl26c a5/ppc_a19 l12t n3 7 (cl) 7 io pl27d wr_n/mpi_rw - f11 - - vdd15 vdd15 - - n5 7 (cl) 8 io pl28d a4/ppc_a18 - m5 7 (cl) - vddio7 vddio7 - - n2 7 (cl) 8 io pl29d a3/ppc_a17 l13c n1 7 (cl) 8 io pl29c a2/ppc_a16 l13t g11 - - vss vss - - p2 7 (cl) 8 io pl30d a1/ppc_a15 l14c p1 7 (cl) 8 io pl30c a0/ppc_a14 l14t f12 - - vdd15 vdd15 - - p3 7 (cl) 8 io pl31d dp0 l15c p4 7 (cl) 8 io pl31c dp1 l15t r4 6 (bl) 1 io pl32d d8 l16c r3 6 (bl) 1 io pl32c vref_6_01 l16t r2 6 (bl) 1 io pl33d d9 l17c r1 6 (bl) 1 io pl33c d10 l17t g12 - - vss vss - - t3 6 (bl) 2 io pl34d - - p5 6 (bl) - vddio6 vddio6 - - t2 6 (bl) 2 io pl34b - l18c t1 6 (bl) 2 io pl34a - l18t u1 6 (bl) 3 io pl35b d11 l19c u2 6 (bl) 3 io pl35a d12 l19t r5 6 (bl) - vddio6 vddio6 - - v1 6 (bl) 3 io pl36b vref_6_03 l20c v2 6 (bl) 3 io pl36a d13 l20t g13 - - vss vss - - w2 6 (bl) 4 io pl37b - l21c w1 6 (bl) 4 io pl37a vref_6_04 l21t y1 6 (bl) 4 io pl39d pll_ck7c/hppll l22c y2 6 (bl) 4 io pl39c pll_ck7t/hppll l22t u3 - - i ptemp ptemp - f13 - - vdd15 vdd15 - - table 44. ORT42G5 484-pin pbgam (fpbga) pinout (continued) 484-pbgam vddio bank vref group i/o pin description additional function 484-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 90 v4 - - io lvds_r lvds_r - v3 - - vdd33 vdd33 - - f17 - - vdd15 vdd15 - - w3 6 (bl) 5 io pb2a dp2 - aa2 6 (bl) 5 io pb2c pll_ck6t/ppll l23t ab2 6 (bl) 5 io pb2d pll_ck6c/ppll l23c aa3 6 (bl) 5 io pb4a vref_6_05 l24t ab3 6 (bl) 5 io pb4b dp3 l24c t5 6 (bl) - vddio6 vddio6 - - h7 - - vss vss - - y4 6 (bl) 6 io pb5c vref_6_06 l25t w4 6 (bl) 6 io pb5d d14 l25c t8 6 (bl) - vddio6 vddio6 - - aa4 6 (bl) 7 io pb6c d15 l26t ab4 6 (bl) 7 io pb6d d16 l26c h8 - - vss vss - - w5 6 (bl) 7 io pb7c d17 l27t y5 6 (bl) 7 io pb7d d18 l27c t9 6 (bl) - vddio6 vddio6 - - aa5 6 (bl) 7 io pb8c vref_6_07 l28t ab5 6 (bl) 7 io pb8d d19 l28c h9 - - vss vss - - v6 6 (bl) 8 io pb9c d20 - g6 - - vdd15 vdd15 - - w6 6 (bl) 8 io pb10c vref_6_08 l29t y6 6 (bl) 8 io pb10d d22 l29c h10 - - vss vss - - aa6 6 (bl) 9 io pb11c d23 l30t ab6 6 (bl) 9 io pb11d d24 l30c u6 6 (bl) - vddio6 vddio6 - - w7 6 (bl) 9 io pb12c vref_6_09 l31t y7 6 (bl) 9 io pb12d d25 l31c h11 - - vss vss - - v7 6 (bl) 10 io pb14a - - u7 6 (bl) - vddio6 vddio6 - - aa7 6 (bl) 10 io pb14c vref_6_10 l32t ab7 6 (bl) 10 io pb14d d28 l32c v8 6 (bl) 11 io pb15a - - h12 - - vss vss - - w8 6 (bl) 11 io pb15c d29 l33t y8 6 (bl) 11 io pb15d d30 l33c u8 6 (bl) 11 io pb16a - - aa8 6 (bl) 11 io pb16c vref_6_11 l34t ab8 6 (bl) 11 io pb16d d31 l34c table 44. ORT42G5 484-pin pbgam (fpbga) pinout (continued) 484-pbgam vddio bank vref group i/o pin description additional function 484-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 91 v9 5 (bc) 1 io pb17a - - w9 5 (bc) 1 io pb17c - l35t y9 5 (bc) 1 io pb17d - l35c u9 5 (bc) 1 io pb18a - - aa9 5 (bc) 1 io pb18c vref_5_01 l36t ab9 5 (bc) 1 io pb18d - l36c g16 - - vdd15 vdd15 - - h13 - - vss vss - - ab10 5 (bc) 2 io pb19a - l37t aa10 5 (bc) 2 io pb19b - l37c w10 5 (bc) 2 io pb19c pbck0t l38t y10 5 (bc) 2 io pb19d pbck0c l38c v10 5 (bc) 2 io pb20a - - u13 5 (bc) - vddio5 vddio5 - - ab11 5 (bc) 2 io pb20c vref_5_02 l39t aa11 5 (bc) 2 io pb20d - l39c u10 5 (bc) 2 io pb21a - - h6 - - vdd15 vdd15 - - y11 5 (bc) 3 io pb21c - l40t w11 5 (bc) 3 io pb21d vref_5_03 l40c u11 5 (bc) 3 io pb22a - - j7 - - vss vss - - ab12 5 (bc) 3 io pb22c - l41t aa12 5 (bc) 3 io pb22d - l41c u12 5 (bc) 3 io pb23a - - y12 5 (bc) 3 io pb23c pbck1t l42t w12 5 (bc) 3 io pb23d pbck1c l42c v11 5 (bc) 3 io pb24a - - j8 - - vss vss - - ab13 5 (bc) 4 io pb24c - l43t aa13 5 (bc) 4 io pb24d - l43c v12 5 (bc) 4 io pb25a - - u14 5 (bc) - vddio5 vddio5 - - ab14 5 (bc) 4 io pb25c - l44t aa14 5 (bc) 4 io pb25d vref_5_04 l44c j9 - - vss vss - - y13 5 (bc) 5 io pb26c - l45t w13 5 (bc) 5 io pb26d vref_5_05 l45c u15 5 (bc) - vddio5 vddio5 - - ab15 5 (bc) 5 io pb27c - l46t aa15 5 (bc) 5 io pb27d - l46c ab16 5 (bc) 6 io pb28c - l47t aa16 5 (bc) 6 io pb28d vref_5_06 l47c h14 - - vdd15 vdd15 - - table 44. ORT42G5 484-pin pbgam (fpbga) pinout (continued) 484-pbgam vddio bank vref group i/o pin description additional function 484-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 92 y14 5 (bc) 6 io pb29c - l48t w14 5 (bc) 6 io pb29d - l48c j10 - - vss vss - - ab17 5 (bc) 7 io pb30c - l49t aa17 5 (bc) 7 io pb30d - l49c u16 5 (bc) - vddio5 vddio5 - - y15 5 (bc) 7 io pb31c vref_5_07 l50t w15 5 (bc) 7 io pb31d - l50c v13 5 (bc) - vddio5 vddio5 - - ab18 5 (bc) 8 io pb33c - l51t aa18 5 (bc) 8 io pb33d vref_5_08 l51c j11 - - vss vss - - v14 5 (bc) 8 io pb34d - - v16 5 (bc) 9 io pb35b - - y16 5 (bc) 9 io pb36c - l52t w16 5 (bc) 9 io pb36d - l52c v15 - - vdd33 vdd33 - - j12 - - vss vss - - h15 - - vdd15 vdd15 - - j13 - - vss vss - - j6 - - vdd15 vdd15 - - j14 - - vss vss - - y17 - - vdd33 vdd33 - - k8 - - vss vss - - j15 - - vdd15 vdd15 - - k7 - - vdd15 vdd15 - - y18 - - vdd33 vdd33 - - k9 - - vss vss - - w21 - - vss vss - - w22 - - vddgb_b vddgb_b - - f18 - - vdd_ana vdd_ana - - v21 - - o rext_b - - v22 - - o rextn_b - - u21 - - i refclkn_b - hsn_1 u22 - - i refclkp_b - hsp_1 e20 - - vss vss - - g17 - - vdd_ana vdd_ana - - g18 - - vdd_ana vdd_ana - - j16 - - vdd_ana vdd_ana - - j17 - - vdd_ana vdd_ana - - t20 - - vddib vddib_bc - - j18 - - vdd_ana vdd_ana - - t21 - - i hdinn_bc - hsn_2 f19 - - vss vss - - table 44. ORT42G5 484-pin pbgam (fpbga) pinout (continued) 484-pbgam vddio bank vref group i/o pin description additional function 484-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 93 t22 - - i hdinp_bc - hsp_2 j19 - - vdd_ana vdd_ana - - f20 - - vss vss - - k16 - - vdd_ana vdd_ana - - r20 - - vddob vddob_bc - - r21 - - o hdoutn_bc - hsn_3 g19 - - vss vss - - r22 - - o hdoutp_bc - hsp_3 p21 - - vddob vddob_bc - - h16 - - vss vss - - p22 - - vddib vddib_bd - - k17 - - vdd_ana vdd_ana - - n22 - - i hdinn_bd - hsn_4 h17 - - vss vss - - n21 - - i hdinp_bd - hsp_4 k18 - - vdd_ana vdd_ana - - h18 - - vss vss - - k19 - - vdd_ana vdd_ana - - p20 - - vddob vddob_bd - - m22 - - o hdoutn_bd - hsn_5 h19 - - vss vss - - m21 - - o hdoutp_bd - hsp_5 n20 - - vddob vddob_bd - - l16 - - vss vss - - l17 - - vss vss - - m20 - - vddob vddob_ad - - l22 - - o hdoutp_ad - hsp_6 l18 - - vss vss - - l21 - - o hdoutn_ad - hsn_6 l20 - - vddob vddob_ad - - n16 - - vdd_ana vdd_ana - - l19 - - vss vss - - n17 - - vdd_ana vdd_ana - - k22 - - i hdinp_ad - hsp_7 m16 - - vss vss - - k21 - - i hdinn_ad - hsn_7 n18 - - vdd_ana vdd_ana - - k20 - - vddib vddib_ad - - m17 - - vss vss - - j20 - - vddob vddob_ac - - j21 - - o hdoutp_ac - hsp_8 m18 - - vss vss - - j22 - - o hdoutn_ac - hsn_8 h20 - - vddob vddob_ac - - table 44. ORT42G5 484-pin pbgam (fpbga) pinout (continued) 484-pbgam vddio bank vref group i/o pin description additional function 484-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 94 n19 - - vdd_ana vdd_ana - - m19 - - vss vss - - p16 - - vdd_ana vdd_ana - - h21 - - i hdinp_ac - hsp_9 r16 - - vss vss - - h22 - - i hdinn_ac - hsn_9 p17 - - vdd_ana vdd_ana - - g20 - - vddib vddib_ac - - p18 - - vdd_ana vdd_ana - - p19 - - vdd_ana vdd_ana - - t17 - - vdd_ana vdd_ana - - t18 - - vdd_ana vdd_ana - - r17 - - vss vss - - g21 - - i refclkp_a - hsp_10 g22 - - i refclkn_a - hsn_10 f21 - - o rextn_a - - f22 - - o rext_a - - u18 - - vdd_ana vdd_ana - - e21 - - vddgb_a vddgb_a - - e22 - - vss vss - - d21 - - o psys_rssig_all - - d22 - - i psys_dobistn - - d20 - - vdd33 vdd33 - - k15 - - vdd15 vdd15 - - k10 - - vss vss - - l7 - - vdd15 vdd15 - - d19 - - i pbist_test_enn - - d18 - - i ploop_test_enn - - l15 - - vdd15 vdd15 - - e17 - - i pasb_pdn - - k11 - - vss vss - - d17 - - vdd33 vdd33 - - m7 - - vdd15 vdd15 - - c21 - - i pasb_resetn - - c22 - - i pasb_tristn - - k12 - - vss vss - - e16 - - i pasb_testclk - - m15 - - vdd15 vdd15 - - c17 - - vdd33 vdd33 - - d16 1 (tc) 7 io pt36d - - c16 1 (tc) 7 io pt36b - - f14 1 (tc) 7 io pt35d - - f15 1 (tc) 7 io pt35b - - e14 1 (tc) 7 io pt34d vref_1_07 - table 44. ORT42G5 484-pin pbgam (fpbga) pinout (continued) 484-pbgam vddio bank vref group i/o pin description additional function 484-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 95 e15 1 (tc) 8 io pt34b - - d15 1 (tc) 8 io pt33d - l53c c15 1 (tc) 8 io pt33c vref_1_08 l53t e12 1 (tc) - vddio1 vddio1 - - c18 1 (tc) 8 io pt32d - l54c c19 1 (tc) 8 io pt32c - l54t k13 - - vss vss - - b21 1 (tc) 9 io pt31d - l55c a21 1 (tc) 9 io pt31c vref_1_09 l55t e13 1 (tc) - vddio1 vddio1 - - d14 1 (tc) 9 io pt30d - l56c c14 1 (tc) 9 io pt30c - l56t k14 - - vss vss - - b20 1 (tc) 9 io pt29d - l57c a20 1 (tc) 9 io pt29c - l57t n7 - - vdd15 vdd15 - - b19 1 (tc) 1 io pt28d - l58c a19 1 (tc) 1 io pt28c - l58t l8 - - vss vss - - d13 1 (tc) 1 io pt27d vref_1_01 l59c c13 1 (tc) 1 io pt27c - l59t e18 1 (tc) - vddio1 vddio1 - - a18 1 (tc) 1 io pt27b - l60c b18 1 (tc) 1 io pt27a - l60t a17 1 (tc) 2 io pt26d - l61c b17 1 (tc) 2 io pt26c vref_1_02 l61t l9 - - vss vss - - d12 1 (tc) 2 io pt25d - l62c c12 1 (tc) 2 io pt25c - l62t e19 1 (tc) - vddio1 vddio1 - - a16 1 (tc) 3 io pt24d - l63c b16 1 (tc) 3 io pt24c vref_1_03 l63t a15 1 (tc) 3 io pt23d - l64c b15 1 (tc) 3 io pt23c - l64t f16 1 (tc) - vddio1 vddio1 - - e11 1 (tc) 3 io pt22d - - l10 - - vss vss - - d11 1 (tc) 4 io pt21d - l65c c11 1 (tc) 4 io pt21c - l65t a14 1 (tc) 4 io pt20d - l66c b14 1 (tc) 4 io pt20c - l66t a13 1 (tc) 4 io pt19d - l67c b13 1 (tc) 4 io pt19c vref_1_04 l67t g14 1 (tc) - vddio1 vddio1 - - table 44. ORT42G5 484-pin pbgam (fpbga) pinout (continued) 484-pbgam vddio bank vref group i/o pin description additional function 484-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 96 l11 - - vss vss - - n15 - - vdd15 vdd15 - - d10 1 (tc) 5 io pt18d ptck1c l68c c10 1 (tc) 5 io pt18c ptck1t l68t a12 1 (tc) 5 io pt17d ptck0c l69c b12 1 (tc) 5 io pt17c ptck0t l69t p6 - - vdd15 vdd15 - - a11 1 (tc) 5 io pt16d vref_1_05 l70c b11 1 (tc) 5 io pt16c - l70t l12 - - vss vss - - d9 1 (tc) 6 io pt15d - l71c c9 1 (tc) 6 io pt15c - l71t g15 1 (tc) - vddio1 vddio1 - - b10 1 (tc) 6 io pt14d - l72c a10 1 (tc) 6 io pt14c vref_1_06 l72t b9 0 (tl) 1 io pt13d mpi_rtry_n l73c a9 0 (tl) 1 io pt13c mpi_ack_n l73t d8 0 (tl) 1 io pt12d m0 l74c c8 0 (tl) 1 io pt12c m1 l74t a22 - - vss vss - - b8 0 (tl) 2 io pt12b mpi_clk l75c a8 0 (tl) 2 io pt12a a21/mpi_burst_n l75t c7 0 (tl) 2 io pt11d m2 l76c d7 0 (tl) 2 io pt11c m3 l76t e9 0 (tl) - vddio0 vddio0 - - e6 0 (tl) 2 io pt11a mpi_tea_n - f6 - - vdd15 vdd15 - - b7 0 (tl) 3 io pt9d vref_0_03 l77c a7 0 (tl) 3 io pt9c - l77t a6 0 (tl) 3 io pt8d d0 l78c b6 0 (tl) 3 io pt8c tms l78t c6 0 (tl) 4 io pt7d a20/mpi_bdip_n l79c d6 0 (tl) 4 io pt7c a19/mpi_tsz1 l79t b1 - - vss vss - - a5 0 (tl) 4 io pt6d a18/mpi_tsz0 l80c b5 0 (tl) 4 io pt6c d3 l80t c5 0 (tl) 5 io pt5d d1 l81c d5 0 (tl) 5 io pt5c d2 l81t b2 - - vss vss - - a4 0 (tl) 5 io pt4d tdi l82c b4 0 (tl) 5 io pt4c tck l82t e10 0 (tl) - vddio0 vddio0 - - b22 - - vss vss - - c4 0 (tl) 6 io pt2d pll_ck1c/ppll l83c table 44. ORT42G5 484-pin pbgam (fpbga) pinout (continued) 484-pbgam vddio bank vref group i/o pin description additional function 484-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 97 d4 0 (tl) 6 io pt2c pll_ck1t/ppll l83t a3 - - o pcfg_mpi_irq cfg_irq_n/mpi_irq_n - b3 - - io pcclk cclk - f7 - - vdd15 vdd15 - - c3 - - io pdone done - e3 - - vdd33 vdd33 - - p15 - - vdd15 vdd15 - - r6 - - vdd15 vdd15 - - r15 - - vdd15 vdd15 - - t4 - - vdd15 vdd15 - - w19 - - vdd15 vdd15 - - y3 - - vdd15 vdd15 - - y19 - - vdd15 vdd15 - - y20 - - vdd15 vdd15 - - t15 - - vdd15 vdd15 - - t16 - - vdd15 vdd15 - - u4 - - vdd15 vdd15 - - t12 - - vdd15 vdd15 - - t13 - - vdd15 vdd15 - - t14 - - vdd15 vdd15 - - t6 - - vdd15 vdd15 - - t7 - - vdd15 vdd15 - - t10 - - vdd15 vdd15 - - t11 - - vdd15 vdd15 - - g5 0 (tl) - vddio0 vddio0 - - h5 0 (tl) - vddio0 vddio0 - - j5 0 (tl) - vddio0 vddio0 - - v17 5 (bc) - vddio5 vddio5 - - w17 5 (bc) - vddio5 vddio5 - - w18 5 (bc) - vddio5 vddio5 - - m6 7 (cl) - vddio7 vddio7 - - n6 7 (cl) - vddio7 vddio7 - - u5 - - vdd15 vdd15 - - u17 - - vdd15 vdd15 - - v5 - - vdd15 vdd15 - - v18 - - vdd15 vdd15 - - r18 - - vss vss - - r19 - - vss vss - - t19 - - vss vss - - u19 - - vss vss - - u20 - - vss vss - - v19 - - vss vss - - v20 - - vss vss - - w20 - - vss vss - - table 44. ORT42G5 484-pin pbgam (fpbga) pinout (continued) 484-pbgam vddio bank vref group i/o pin description additional function 484-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 98 y21 - - vss vss - - y22 - - vss vss - - l13 - - vss vss - - l14 - - vss vss - - m8 - - vss vss - - m9 - - vss vss - - m10 - - vss vss - - m11 - - vss vss - - m12 - - vss vss - - m13 - - vss vss - - m14 - - vss vss - - n8 - - vss vss - - n9 - - vss vss - - n10 - - vss vss - - n11 - - vss vss - - n12 - - vss vss - - n13 - - vss vss - - n14 - - vss vss - - p7 - - vss vss - - p8 - - vss vss - - p9 - - vss vss - - p10 - - vss vss - - p11 - - vss vss - - p12 - - vss vss - - p13 - - vss vss - - p14 - - vss vss - - r7 - - vss vss - - r8 - - vss vss - - r9 - - vss vss - - r10 - - vss vss - - r11 - - vss vss - - r12 - - vss vss - - r13 - - vss vss - - r14 - - vss vss - - aa1 - - vss vss - - aa19 - - vss vss - - aa20 - - vss vss - - aa21 - - vss vss - - aa22 - - vss vss - - ab1 - - vss vss - - ab19 - - vss vss - - ab20 - - vss vss - - ab21 - - vss vss - - ab22 - - vss vss - - table 44. ORT42G5 484-pin pbgam (fpbga) pinout (continued) 484-pbgam vddio bank vref group i/o pin description additional function 484-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 99 table 45. ort82g5 680-pin pbgam (fpbga) pinout 680-pbgam v dd io bank vref group i/o pin description additional function 680-pbgam ab20 vss vss c3 v dd 33 v dd 33 e4 o prd_data rd_data/tdo f5 i preset_n reset_n g5 i prd_cfg_n rd_cfg_n d3 i pprgrm_n prgrm_n a2 0 (tl) v dd io0 v dd io0 f4 0 (tl) 7 io pl2d pll_ck0c/hppll l21c_a0 g4 0 (tl) 7 io pl2c pll_ck0t/hppll l21t_a0 b3 0 (tl) v dd io0 v dd io0 c2 0 (tl) 7 io pl3d l22c_d0 b1 0 (tl) 7 io pl3c vref_0_07 l22t_d0 a1 vss v ss j5 0 (tl) 7 io pl4d d5 l23c_a0 h5 0 (tl) 7 io pl4c d6 l23t_a0 b7 0 (tl) v dd io0 v dd io0 e3 0 (tl) 8 io pl4b l24c_a0 f3 0 (tl) 8 io pl4a vref_0_08 l24t_a0 c1 0 (tl) 8 io pl5d hdc l25c_d0 d2 0 (tl) 8 io pl5c ldc_n l25t_d0 a34 v ss v ss g3 0 (tl) 8 io pl5b l26c_d0 h4 0 (tl) 8 io pl5a l26t_d0 e2 0 (tl) 9 io pl6d testcfg l27c_d0 d1 0 (tl) 9 io pl6c d7 l27t_d0 c5 0 (tl) v dd io0 v dd io0 f2 0 (tl) 9 io pl7d vref_0_09 l28c_d0 e1 0 (tl) 9 io pl7c a17/ppc_a31 l28t_d0 aa13 v ss v ss j4 0 (tl) 9 io pl7b l29c_d0 k5 0 (tl) 9 io pl7a l29t_d0 h3 0 (tl) 9 io pl8d cs0_n l30c_d0 g2 0 (tl) 9 io pl8c cs1 l30t_d0 c9 0 (tl) v dd io0 v dd io0 l5 0 (tl) 9 io pl8b l31c_d0 k4 0 (tl) 9 io pl8a l31t_d0 h2 0 (tl) 10 io pl9d l32c_d0 j3 0 (tl) 10 io pl9c l32t_d0 aa14 v ss v ss m5 0 (tl) 10 io pl9b f1 0 (tl) 10 io pl10d init_n l33c_a0 g1 0 (tl) 10 io pl10c dout l33t_a0 k3 0 (tl) 10 io pl11d vref_0_10 l34c_d0 j2 0 (tl) 10 io pl11c a16/ppc_a30 l34t_d0 lattice semiconductor orca ORT42G5 and ort82g5 data sheet 100 aa15 v ss v ss l4 0 (tl) 10 io pl11b n5 7 (cl) 1 io pl12d a15/ppc_a29 l1c_d0 m4 7 (cl) 1 io pl12c a14/ppc_a28 l1t_d0 aa3 7 (cl) v dd io7 v dd io7 l3 7 (cl) 1 io pl12b l2c_d0 k2 7 (cl) 1 io pl12a l2t_d0 h1 7 (cl) 1 io pl13d vref_7_01 l3c_a0 j1 7 (cl) 1 io pl13c d4 l3t_a0 v18 v ss v ss n4 7 (cl) 2 io pl13b l4c_d0 p5 7 (cl) 2 io pl13a l4t_d0 m3 7 (cl) 2 io pl14d rdy/busy_n/rclk l5c_d0 l2 7 (cl) 2 io pl14c vref_7_02 l5t_d0 ac2 7 (cl) v dd io7 v dd io7 k1 7 (cl) 2 io pl14b l6c_a0 l1 7 (cl) 2 io pl14a l6t_a0 p4 7 (cl) 2 io pl15d a13/ppc_a27 l7c_a0 p3 7 (cl) 2 io pl15c a12/ppc_a26 l7t_a0 v19 v ss v ss m2 7 (cl) 2 io pl15b l8c_a0 m1 7 (cl) 2 io pl15a l8t_a0 n2 7 (cl) 3 io pl16d l9c_a0 n1 7 (cl) 3 io pl16c l9t_a0 n3 7 (cl) v dd io7 v dd io7 r4 7 (cl) 3 io pl16b p2 7 (cl) 3 io pl17d a11/ppc_a25 l10c_d0 r3 7 (cl) 3 io pl17c vref_7_03 l10t_d0 w16 v ss v ss r5 7 (cl) 3 io pl17b p1 7 (cl) 3 io pl18d l11c_a0 r1 7 (cl) 3 io pl18c l11t_a0 t5 7 (cl) 3 io pl18b l12c_a0 t4 7 (cl) 3 io pl18a l12t_a0 t3 7 (cl) 4 io pl19d rd_n/mpi_strb_n l13c_a0 t2 7 (cl) 4 io pl19c vref_7_04 l13t_a0 w17 v ss v ss u1 7 (cl) 4 io pl19b l14c_a0 t1 7 (cl) 4 io pl19a l14t_a0 u4 7 (cl) 4 io pl20d plck0c l15c_a0 u5 7 (cl) 4 io pl20c plck0t l15t_a0 r2 7 (cl) v dd io7 v dd io7 u2 7 (cl) 4 io pl20b l16c_d0 v1 7 (cl) 4 io pl20a l16t_d0 table 45. ort82g5 680-pin pbgam (fpbga) pinout (continued) 680-pbgam v dd io bank vref group i/o pin description additional function 680-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 101 w18 v ss v ss v2 7 (cl) 5 io pl21d a10/ppc_a24 l17c_a0 v3 7 (cl) 5 io pl21c a9/ppc_a23 l17t_a0 w19 v ss v ss v4 7 (cl) 5 io pl21b l18c_a0 v5 7 (cl) 5 io pl21a l18t_a0 w4 7 (cl) 5 io pl22d a8/ppc_a22 l19c_a0 w3 7 (cl) 5 io pl22c vref_7_05 l19t_a0 w1 7 (cl) 5 io pl22b l20c_a0 y1 7 (cl) 5 io pl22a l20t_a0 y2 7 (cl) 5 io pl23d l21c_d0 aa1 7 (cl) 5 io pl23c l21t_d0 y13 v ss v ss y4 7 (cl) 5 io pl23b l22c_a0 y3 7 (cl) 5 io pl23a l22t_a0 y5 7 (cl) 6 io pl24d plck1c l23c_a0 w5 7 (cl) 6 io pl24c plck1t l23t_a0 u3 7 (cl) v dd io7 v dd io7 ab1 7 (cl) 6 io pl24b l24c_d0 aa2 7 (cl) 6 io pl24a l24t_d0 ab2 7 (cl) 6 io pl25d vref_7_06 l25c_d0 ac1 7 (cl) 6 io pl25c a7/ppc_a21 l25t_d0 y14 v ss v ss aa4 7 (cl) 6 io pl25b ab4 7 (cl) 6 io pl26d a6/ppc_a20 l26c_a0 ab3 7 (cl) 6 io pl26c a5/ppc_a19 l26t_a0 w2 7 (cl) v dd io7 v dd io7 ad1 7 (cl) 7 io pl26b ae1 7 (cl) 7 io pl27d wr_n/mpi_rw l27c_d0 ad2 7 (cl) 7 io pl27c vref_7_07 l27t_d0 ac3 7 (cl) 7 io pl27b l28c_a0 ac4 7 (cl) 7 io pl27a l28t_a0 af1 7 (cl) 8 io pl28d a4/ppc_a18 l29c_d0 ae2 7 (cl) 8 io pl28c vref_7_08 l29t_d0 ab5 7 (cl) 8 io pl29d a3/ppc_a17 l30c_a0 aa5 7 (cl) 8 io pl29c a2/ppc_a16 l30t_a0 y15 v ss v ss ad3 7 (cl) 8 io pl29b ag1 7 (cl) 8 io pl30d a1/ppc_a15 l31c_d0 af2 7 (cl) 8 io pl30c a0/ppc_a14 l31t_d0 ad4 7 (cl) 8 io pl30b l32c_d0 ae3 7 (cl) 8 io pl30a l32t_d0 ad5 7 (cl) 8 io pl31d dp0 l33c_a0 ac5 7 (cl) 8 io pl31c dp1 l33t_a0 table 45. ort82g5 680-pin pbgam (fpbga) pinout (continued) 680-pbgam v dd io bank vref group i/o pin description additional function 680-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 102 y20 v ss v ss ag2 7 (cl) 8 io pl31b l34c_d0 ah1 7 (cl) 8 io pl31a l34t_d0 af3 6 (bl) 1 io pl32d d8 l1c_a0 ag3 6 (bl) 1 io pl32c vref_6_01 l1t_a0 al7 6 (bl) v dd io6 v dd io6 ae4 6 (bl) 1 io pl32b l2c_a0 af4 6 (bl) 1 io pl32a l2t_a0 ae5 6 (bl) 1 io pl33d d9 l3c_a0 af5 6 (bl) 1 io pl33c d10 l3t_a0 r21 v ss v ss aj1 6 (bl) 2 io pl34d l4c_d0 ah2 6 (bl) 2 io pl34c vref_6_02 l4t_d0 am5 6 (bl) v dd io6 v dd io6 ak1 6 (bl) 2 io pl34b l5c_d0 aj2 6 (bl) 2 io pl34a l5t_d0 r22 v ss v ss ag4 6 (bl) 3 io pl35b d11 l6c_d0 ah3 6 (bl) 3 io pl35a d12 l6t_d0 al1 6 (bl) 3 io pl36d l7c_d0 ak2 6 (bl) 3 io pl36c l7t_d0 am9 6 (bl) v dd io6 v dd io6 am1 6 (bl) 3 io pl36b vref_6_03 l8c_d0 al2 6 (bl) 3 io pl36a d13 l8t_d0 aj3 6 (bl) 4 io pl37d t16 v ss v ss aj4 6 (bl) 4 io pl37b l9c_a0 ah4 6 (bl) 4 io pl37a vref_6_04 l9t_a0 ak3 6 (bl) 4 io pl38c an2 6 (bl) v dd io6 v dd io6 ag5 6 (bl) 4 io pl38b l10c_a0 ah5 6 (bl) 4 io pl38a l10t_a0 an1 6 (bl) 4 io pl39d pll_ck7c/hppll l11c_d0 am2 6 (bl) 4 io pl39c pll_ck7t/hppll l11t_d0 t17 v ss v ss al3 6 (bl) 4 io pl39b l12c_d0 ak4 6 (bl) 4 io pl39a l12t_d0 t18 v ss v ss am3 i ptemp ptemp an3 6 (bl) v dd io6 v dd io6 aj5 io lvds_r lvds_r al4 v dd 33 v dd 33 t19 v ss v ss ak5 v dd 33 v dd 33 table 45. ort82g5 680-pin pbgam (fpbga) pinout (continued) 680-pbgam v dd io bank vref group i/o pin description additional function 680-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 103 am4 6 (bl) 5 io pb2a dp2 l13t_d0 al5 6 (bl) 5 io pb2b l13c_d0 an7 6 (bl) v dd io6 v dd io6 ap3 6 (bl) 5 io pb2c pll_ck6t/ppll l14t_a0 ap4 6 (bl) 5 io pb2d pll_ck6c/ppll l14c_a0 an4 6 (bl) 5 io pb3b u16 v ss v ss ak6 6 (bl) 5 io pb3c l15t_a0 ak7 6 (bl) 5 io pb3d l15c_a0 al6 6 (bl) 5 io pb4a vref_6_05 l16t_a0 am6 6 (bl) 5 io pb4b dp3 l16c_a0 ap1 6 (bl) v dd io6 v dd io6 an5 6 (bl) 6 io pb4c l17t_a0 ap5 6 (bl) 6 io pb4d l17c_a0 ak8 6 (bl) 6 io pb5b u17 v ss v ss ap6 6 (bl) 6 io pb5c vref_6_06 l18t_d0 ap7 6 (bl) 6 io pb5d d14 l18c_d0 am7 6 (bl) 6 io pb6a l19t_d0 an6 6 (bl) 6 io pb6b l19c_d0 ap2 6 (bl) v dd io6 v dd io6 al8 6 (bl) 7 io pb6c d15 l20t_a0 al9 6 (bl) 7 io pb6d d16 l20c_a0 ak9 6 (bl) 7 io pb7b u18 v ss v ss an8 6 (bl) 7 io pb7c d17 l21t_a0 am8 6 (bl) 7 io pb7d d18 l21c_a0 an9 6 (bl) 7 io pb8a l22t_d0 ap8 6 (bl) 7 io pb8b l22c_d0 ak10 6 (bl) 7 io pb8c vref_6_07 l23t_a0 al10 6 (bl) 7 io pb8d d19 l23c_a0 ap9 6 (bl) 8 io pb9b u19 v ss v ss am10 6 (bl) 8 io pb9c d20 l24t_a0 am11 6 (bl) 8 io pb9d d21 l24c_a0 ak11 6 (bl) 8 io pb10b an10 6 (bl) 8 io pb10c vref_6_08 l25t_a0 ap10 6 (bl) 8 io pb10d d22 l25c_a0 an11 6 (bl) 9 io pb11a l26t_a0 ap11 6 (bl) 9 io pb11b l26c_a0 v16 v ss v ss al12 6 (bl) 9 io pb11c d23 l27t_a0 ak12 6 (bl) 9 io pb11d d24 l27c_a0 an12 6 (bl) 9 io pb12a l28t_a0 table 45. ort82g5 680-pin pbgam (fpbga) pinout (continued) 680-pbgam v dd io bank vref group i/o pin description additional function 680-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 104 am12 6 (bl) 9 io pb12b l28c_a0 ap12 6 (bl) 9 io pb12c vref_6_09 l29t_a0 ap13 6 (bl) 9 io pb12d d25 l29c_a0 am13 6 (bl) 9 io pb13a l30t_d0 an14 6 (bl) 9 io pb13b l30c_d0 v17 v ss v ss ap14 6 (bl) 10 io pb13c d26 l31t_a0 ap15 6 (bl) 10 io pb13d d27 l31c_a0 ak13 6 (bl) 10 io pb14a l32t_a0 ak14 6 (bl) 10 io pb14b l32c_a0 am14 6 (bl) 10 io pb14c vref_6_10 l33t_a0 al14 6 (bl) 10 io pb14d d28 l33c_a0 ap17 6 (bl) 11 io pb15a l34t_a0 ap16 6 (bl) 11 io pb15b l34c_a0 am15 6 (bl) 11 io pb15c d29 l35t_d0 an16 6 (bl) 11 io pb15d d30 l35c_d0 am17 6 (bl) 11 io pb16a l36t_a0 am16 6 (bl) 11 io pb16b l36c_a0 ap18 6 (bl) 11 io pb16c vref_6_11 l37t_a0 ap19 6 (bl) 11 io pb16d d31 l37c_a0 al16 5 (bc) 1 io pb17a l1t_d0 ak15 5 (bc) 1 io pb17b l1c_d0 n22 v ss v ss an18 5 (bc) 1 io pb17c l2t_a0 an19 5 (bc) 1 io pb17d l2c_a0 ap20 5 (bc) 1 io pb18a l3t_a0 ap21 5 (bc) 1 io pb18b l3c_a0 al17 5 (bc) 1 io pb18c vref_5_01 l4t_d0 ak16 5 (bc) 1 io pb18d l4c_d0 p13 v ss v ss am19 5 (bc) 2 io pb19a l5t_a0 am18 5 (bc) 2 io pb19b l5c_a0 p14 v ss v ss an20 5 (bc) 2 io pb19c pbck0t l6t_a0 am20 5 (bc) 2 io pb19d pbck0c l6c_a0 ak17 5 (bc) 2 io pb20a l7t_d0 al18 5 (bc) 2 io pb20b l7c_d0 al11 5 (bc) v dd io5 v dd io5 ap22 5 (bc) 2 io pb20c vref_5_02 l8t_d0 an21 5 (bc) 2 io pb20d l8c_d0 am22 5 (bc) 2 io pb21a l9t_a0 am21 5 (bc) 2 io pb21b l9c_a0 ap23 5 (bc) 3 io pb21c l10t_d0 an22 5 (bc) 3 io pb21d vref_5_03 l10c_d0 table 45. ort82g5 680-pin pbgam (fpbga) pinout (continued) 680-pbgam v dd io bank vref group i/o pin description additional function 680-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 105 al19 5 (bc) 3 io pb22a l11t_d0 ak18 5 (bc) 3 io pb22b l11c_d0 p15 v ss v ss ap24 5 (bc) 3 io pb22c l12t_d0 an23 5 (bc) 3 io pb22d l12c_d0 ap25 5 (bc) 3 io pb23a l13t_a0 ap26 5 (bc) 3 io pb23b l13c_a0 al13 5 (bc) v dd io5 v dd io5 al20 5 (bc) 3 io pb23c pbck1t l14t_d0 ak19 5 (bc) 3 io pb23d pbck1c l14c_d0 ak20 5 (bc) 3 io pb24a l15t_d0 al21 5 (bc) 3 io pb24b l15c_d0 p20 v ss v ss an24 5 (bc) 4 io pb24c l16t_d0 am23 5 (bc) 4 io pb24d l16c_d0 an26 5 (bc) 4 io pb25a l17t_a0 an25 5 (bc) 4 io pb25b l17c_a0 al15 5 (bc) v dd io5 v dd io5 ak21 5 (bc) 4 io pb25c l18t_d0 al22 5 (bc) 4 io pb25d vref_5_04 l18c_d0 am24 5 (bc) 4 io pb26a l19t_d0 al23 5 (bc) 4 io pb26b l19c_d0 p21 v ss v ss ap27 5 (bc) 5 io pb26c l20t_a0 an27 5 (bc) 5 io pb26d vref_5_05 l20c_a0 al24 5 (bc) 5 io pb27a l21t_d0 am25 5 (bc) 5 io pb27b l21c_d0 an13 5 (bc) v dd io5 v dd io5 ap28 5 (bc) 5 io pb27c l22t_a0 ap29 5 (bc) 5 io pb27d l22c_a0 an29 5 (bc) 6 io pb28b p22 v ss v ss am27 5 (bc) 6 io pb28c l23t_d0 an28 5 (bc) 6 io pb28d vref_5_06 l23c_d0 am26 5 (bc) 6 io pb29b ak22 5 (bc) 6 io pb29c l24t_a0 ak23 5 (bc) 6 io pb29d l24c_a0 al25 5 (bc) 7 io pb30b r13 v ss v ss ap30 5 (bc) 7 io pb30c l25t_a0 ap31 5 (bc) 7 io pb30d l25c_a0 ak24 5 (bc) 7 io pb31b an15 5 (bc) v dd io5 v dd io5 am29 5 (bc) 7 io pb31c vref_5_07 l26t_a0 table 45. ort82g5 680-pin pbgam (fpbga) pinout (continued) 680-pbgam v dd io bank vref group i/o pin description additional function 680-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 106 am28 5 (bc) 7 io pb31d l26c_a0 an30 5 (bc) 7 io pb32b r14 v ss v ss ak25 5 (bc) 7 io pb32c l27t_d0 al26 5 (bc) 7 io pb32d l27c_d0 an17 5 (bc) v dd io5 v dd io5 al27 5 (bc) 8 io pb33c l28t_a0 al28 5 (bc) 8 io pb33d vref_5_08 l28c_a0 an31 5 (bc) 8 io pb34b r15 v ss v ss ak26 5 (bc) 8 io pb34d am30 5 (bc) 9 io pb35b al29 5 (bc) 9 io pb35d vref_5_09 ak27 5 (bc) 9 io pb36b r20 v ss v ss al30 5 (bc) 9 io pb36c l29t_d0 ak29 5 (bc) 9 io pb36d l29c_d0 ak28 v dd 33 v dd 33 aa16 v dd 15 v dd 15 ap32 io pschar_ldio9 ap33 io pschar_ldio8 an32 io pschar_ldio7 am31 io pschar_ldio6 aa17 v dd 15 v dd 15 am32 v dd 33 v dd 33 al31 io pschar_ldio5 am33 io pschar_ldio4 aa18 v dd 15 v dd 15 ak30 io pschar_ldio3 al32 io pschar_ldio2 aa19 v dd 15 v dd 15 ab16 v dd 15 v dd 15 ak31 v dd 33 v dd 33 aj30 io pschar_ldio1 ak33 io pschar_ldio0 ak34 io pschar_ckio1 aj31 io pschar_ckio0 aj33 io pschar_xck aj34 io pschar_wdsync ah30 io pschar_cv ah31 io pschar_bytsync ah32 o atmout_b (no connect) ah33 v ss v ss ah34 v dd gb_b v dd gb_b table 45. ort82g5 680-pin pbgam (fpbga) pinout (continued) 680-pbgam v dd io bank vref group i/o pin description additional function 680-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 107 aa32 vdd_ana vdd_ana af30 rext_b af31 rextn_b ae30 i refclkn_b ae31 i refclkp_b ab32 v ss v ss ad30 v dd ib v dd ib_ba ad32 vdd_ana vdd_ana af33 i hdinn_ba ac32 v ss v ss af34 i hdinp_ba ae32 vdd_ana vdd_ana ad31 v ss v ss k32 vdd_ana vdd_ana ae33 o hdoutn_ba af32 v ss v ss ae34 o hdoutp_ba ac30 v dd ob v dd ob_ba ag30 v ss v ss ab30 v dd ib v dd ib_bb ad33 i hdinn_bb ag31 v ss v ss ad34 i hdinp_bb ac31 v ss v ss ac33 o hdoutn_bb ag32 v ss v ss ac34 o hdoutp_bb ab31 v dd ob v dd ob_bb ag33 v ss v ss aa30 v dd ib v dd ib_bc ab33 i hdinn_bc ag34 v ss v ss ab34 i hdinp_bc aa31 v ss v ss y30 v dd ob v dd ob_bc aa33 o hdoutn_bc h30 v ss v ss aa34 o hdoutp_bc y31 v dd ob v dd ob_bc h31 v ss v ss w30 v dd ib v dd ib_bd y33 i hdinn_bd h32 v ss v ss y34 i hdinp_bd table 45. ort82g5 680-pin pbgam (fpbga) pinout (continued) 680-pbgam v dd io bank vref group i/o pin description additional function 680-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 108 w31 v ss v ss v30 v dd ob v dd ob_bd w33 o hdoutn_bd h33 v ss v ss w34 o hdoutp_bd v31 v dd ob v dd ob_bd h34 v ss v ss j32 v ss v ss u31 v dd ob v dd ob_ad t34 o hdoutp_ad m32 v ss v ss t33 o hdoutn_ad u30 v dd ob v dd ob_ad t31 v ss v ss r34 i hdinp_ad n32 v ss v ss r33 i hdinn_ad t30 v dd ib v dd ib_ad u32 v ss v ss r31 v dd ob v dd ob_ac p34 o hdoutp_ac u33 v ss v ss p33 o hdoutn_ac r30 v dd ob v dd ob_ac p31 v ss v ss n34 i hdinp_ac u34 v ss v ss n33 i hdinn_ac p30 v dd ib v dd ib_ac v32 v ss v ss m34 o hdoutp_ab v33 v ss v ss m33 o hdoutn_ab n31 v dd ob v dd ob_ab m31 v ss v ss l34 i hdinp_ab v34 v ss v ss l33 i hdinn_ab n30 v dd ib v dd ib_ab k34 o hdoutp_aa k33 o hdoutn_aa m30 v dd ob v dd ob_aa l32 vdd_ana vdd_ana l31 v ss v ss table 45. ort82g5 680-pin pbgam (fpbga) pinout (continued) 680-pbgam v dd io bank vref group i/o pin description additional function 680-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 109 p32 vdd_ana vdd_ana j34 i hdinp_aa j33 i hdinn_aa r32 vdd_ana vdd_ana l30 v dd ib v dd ib_aa k31 refclkp_a k30 refclkn_a j31 o rextn_a j30 o rext_a y32 vdd_ana vdd_ana g34 v dd gb_a v dd gb_a g33 v ss v ss g32 o atmout_a (no connect) g31 i preserve01 (no connect) f33 i preserve02 (no connect) g30 i preserve03 (no connect) f31 o psys_rssig_all f30 i psys_dobistn e31 v dd 33 v dd 33 ab17 v dd 15 v dd 15 ab18 v dd 15 v dd 15 d32 i pbist_test_enn e30 i ploop_test_enn ab19 v dd 15 v dd 15 d31 i pasb_pdn c32 i pmp_testclk c31 v dd 33 v dd 33 aj32 v dd 15 v dd 15 b32 i pasb_resetn a33 i pasb_tristn b31 i pmp_testclk_enn a32 i pasb_testclk ak32 v dd 15 v dd 15 ab21 v ss v ss a31 v dd 33 v dd 33 b30 1 (tc) 7 io pt36d ab22 v ss v ss c30 1 (tc) 7 io pt36b d30 1 (tc) 7 io pt35d b13 1 (tc) v dd io1 v dd io1 e29 1 (tc) 7 io pt35b e28 1 (tc) 7 io pt34d vref_1_07 an33 v ss vss d29 1 (tc) 8 io pt34b table 45. ort82g5 680-pin pbgam (fpbga) pinout (continued) 680-pbgam v dd io bank vref group i/o pin description additional function 680-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 110 b29 1 (tc) 8 io pt33d l1c_a0 c29 1 (tc) 8 io pt33c vref_1_08 l1t_a0 b15 1 (tc) v dd io1 v dd io1 e27 1 (tc) 8 io pt32d l2c_a0 e26 1 (tc) 8 io pt32c l2t_a0 ap34 vss vss a30 1 (tc) 8 io pt32b a29 1 (tc) 9 io pt31d l3c_d3 e25 1 (tc) 9 io pt31c vref_1_09 l3t_d3 b17 1 (tc) v dd io1 v dd io1 e24 1 (tc) 9 io pt31a b28 1 (tc) 9 io pt30d l4c_a0 c28 1 (tc) 9 io pt30c l4t_a0 b2 vss vss d28 1 (tc) 9 io pt30a c27 1 (tc) 9 io pt29d l5c_a0 d27 1 (tc) 9 io pt29c l5t_a0 e23 1 (tc) 9 io pt29b l6c_a0 e22 1 (tc) 9 io pt29a l6t_a0 d26 1 (tc) 1 io pt28d l7c_a0 d25 1 (tc) 1 io pt28c l7t_a0 b33 vss vss d24 1 (tc) 1 io pt28b l8c_a0 d23 1 (tc) 1 io pt28a l8t_a0 c26 1 (tc) 1 io pt27d vref_1_01 l9c_a0 c25 1 (tc) 1 io pt27c l9t_a0 d11 1 (tc) v dd io1 v dd io1 e21 1 (tc) 1 io pt27b l10c_a0 e20 1 (tc) 1 io pt27a l10t_a0 d22 1 (tc) 2 io pt26d l11c_a0 d21 1 (tc) 2 io pt26c vref_1_02 l11t_a0 e34 vss vss a28 1 (tc) 2 io pt26b b26 1 (tc) 2 io pt25d l12c_a0 b25 1 (tc) 2 io pt25c l12t_a0 d13 1 (tc) v dd io1 v dd io1 b27 1 (tc) 2 io pt25b a27 1 (tc) 3 io pt24d l13c_a0 a26 1 (tc) 3 io pt24c vref_1_03 l13t_a0 n13 vss vss c24 1 (tc) 3 io pt24b c22 1 (tc) 3 io pt23d l14c_a0 c23 1 (tc) 3 io pt23c l14t_a0 d15 1 (tc) v dd io1 v dd io1 table 45. ort82g5 680-pin pbgam (fpbga) pinout (continued) 680-pbgam v dd io bank vref group i/o pin description additional function 680-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 111 b24 1 (tc) 3 io pt23b d20 1 (tc) 3 io pt22d l15c_a0 d19 1 (tc) 3 io pt22c l15t_a0 n14 vss vss e19 1 (tc) 3 io pt22b l16c_a0 e18 1 (tc) 3 io pt22a l16t_a0 c21 1 (tc) 4 io pt21d l17c_a0 c20 1 (tc) 4 io pt21c l17t_a0 a25 1 (tc) 4 io pt21b l18c_a0 a24 1 (tc) 4 io pt21a l18t_a0 b23 1 (tc) 4 io pt20d l19c_a0 a23 1 (tc) 4 io pt20c l19t_a0 n15 vss vss e17 1 (tc) 4 io pt20b l20c_a0 e16 1 (tc) 4 io pt20a l20t_a0 b22 1 (tc) 4 io pt19d l21c_a0 b21 1 (tc) 4 io pt19c vref_1_04 l21t_a0 c18 1 (tc) 4 io pt19b l22c_a0 c19 1 (tc) 4 io pt19a l22t_a0 n20 vss vss a22 1 (tc) 5 io pt18d ptck1c l23c_a0 a21 1 (tc) 5 io pt18c ptck1t l23t_a0 n21 vss vss d17 1 (tc) 5 io pt18b l24c_a0 d18 1 (tc) 5 io pt18a l24t_a0 b20 1 (tc) 5 io pt17d ptck0c l25c_a0 b19 1 (tc) 5 io pt17c ptck0t l25t_a0 a20 1 (tc) 5 io pt17b l26c_a0 a19 1 (tc) 5 io pt17a l26t_a0 a18 1 (tc) 5 io pt16d vref_1_05 l27c_a0 b18 1 (tc) 5 io pt16c l27t_a0 y21 vss vss c17 1 (tc) 5 io pt16b l28c_d0 d16 1 (tc) 5 io pt16a l28t_d0 a17 1 (tc) 6 io pt15d l29c_d0 b16 1 (tc) 6 io pt15c l29t_d0 e15 1 (tc) 6 io pt15b l30c_a0 e14 1 (tc) 6 io pt15a l30t_a0 a16 1 (tc) 6 io pt14d l31c_a0 a15 1 (tc) 6 io pt14c vref_1_06 l31t_a0 y22 vss vss d14 1 (tc) 6 io pt14b c16 0 (tl) 1 io pt13d mpi_rtry_n l1c_a0 c15 0 (tl) 1 io pt13c mpi_ack_n l1t_a0 table 45. ort82g5 680-pin pbgam (fpbga) pinout (continued) 680-pbgam v dd io bank vref group i/o pin description additional function 680-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 112 d7 0 (tl) v dd io0 v dd io0 c14 0 (tl) 1 io pt13b l2c_a0 b14 0 (tl) 1 io pt13a vref_0_01 l2t_a0 a14 0 (tl) 1 io pt12d m0 l3c_a0 a13 0 (tl) 1 io pt12c m1 l3t_a0 aa20 vss vss e12 0 (tl) 2 io pt12b mpi_clk l4c_a0 e13 0 (tl) 2 io pt12a a21/mpi_burst_n l4t_a0 c13 0 (tl) 2 io pt11d m2 l5c_a0 c12 0 (tl) 2 io pt11c m3 l5t_a0 b12 0 (tl) 2 io pt11b vref_0_02 l6c_a0 a12 0 (tl) 2 io pt11a mpi_tea_n l6t_a0 d12 0 (tl) 3 io pt10d l7c_d0 c11 0 (tl) 3 io pt10c l7t_d0 b11 0 (tl) 3 io pt10b a11 0 (tl) 3 io pt9d vref_0_03 l8c_a0 a10 0 (tl) 3 io pt9c l8t_a0 aa21 vss vss b10 0 (tl) 3 io pt9b e11 0 (tl) 3 io pt8d d0 l9c_d0 d10 0 (tl) 3 io pt8c tms l9t_d0 c10 0 (tl) 3 io pt8b a9 0 (tl) 4 io pt7d a20/mpi_bdip_n l10c_a0 b9 0 (tl) 4 io pt7c a19/mpi_tsz1 l10t_a0 aa22 vss vss e10 0 (tl) 4 io pt7b a8 0 (tl) 4 io pt6d a18/mpi_tsz0 l11c_a0 b8 0 (tl) 4 io pt6c d3 l11t_a0 d9 0 (tl) 4 io pt6b vref_0_04 l12c_d0 c8 0 (tl) 4 io pt6a l12t_d0 e9 0 (tl) 5 io pt5d d1 l13c_d0 d8 0 (tl) 5 io pt5c d2 l13t_d0 ab13 vss vss a7 0 (tl) 5 io pt5b l14c_a0 a6 0 (tl) 5 io pt5a vref_0_05 l14t_a0 c7 0 (tl) 5 io pt4d tdi l15c_d0 b6 0 (tl) 5 io pt4c tck l15t_d0 e8 0 (tl) 5 io pt4b l16c_a0 e7 0 (tl) 5 io pt4a l16t_a0 a5 0 (tl) 6 io pt3d l17c_a0 b5 0 (tl) 6 io pt3c vref_0_06 l17t_a0 ab14 vss vss c6 0 (tl) 6 io pt3b l18c_a0 d6 0 (tl) 6 io pt3a l18t_a0 table 45. ort82g5 680-pin pbgam (fpbga) pinout (continued) 680-pbgam v dd io bank vref group i/o pin description additional function 680-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 113 c4 0 (tl) 6 io pt2d pll_ck1c/ppll l19c_a0 b4 0 (tl) 6 io pt2c pll_ck1t/ppll l19t_a0 a4 0 (tl) 6 io pt2b l20c_a0 a3 0 (tl) 6 io pt2a l20t_a0 d5 o pcfg_mpi_irq cfg_irq_n/mpi_irq_n e6 io pcclk cclk d4 io pdone done e5 v dd 33 v dd 33 ab15 vss vss al33 v dd 15 v dd 15 al34 v dd 15 v dd 15 am34 v dd 15 v dd 15 an34 v dd 15 v dd 15 b34 v dd 15 v dd 15 c33 v dd 15 v dd 15 c34 v dd 15 v dd 15 d33 v dd 15 v dd 15 d34 v dd 15 v dd 15 e32 v dd 15 v dd 15 e33 v dd 15 v dd 15 f32 v dd 15 v dd 15 f34 v dd 15 v dd 15 n16 v dd 15 v dd 15 n17 v dd 15 v dd 15 n18 v dd 15 v dd 15 n19 v dd 15 v dd 15 p16 v dd 15 v dd 15 p17 v dd 15 v dd 15 p18 v dd 15 v dd 15 p19 v dd 15 v dd 15 r16 v dd 15 v dd 15 r17 v dd 15 v dd 15 r18 v dd 15 v dd 15 r19 v dd 15 v dd 15 t13 v dd 15 v dd 15 t14 v dd 15 v dd 15 t15 v dd 15 v dd 15 t20 v dd 15 v dd 15 t21 v dd 15 v dd 15 t22 v dd 15 v dd 15 u13 v dd 15 v dd 15 u14 v dd 15 v dd 15 u15 v dd 15 v dd 15 u20 v dd 15 v dd 15 table 45. ort82g5 680-pin pbgam (fpbga) pinout (continued) 680-pbgam v dd io bank vref group i/o pin description additional function 680-pbgam lattice semiconductor orca ORT42G5 and ort82g5 data sheet 114 package thermal characteristics summary there are three thermal parameters that are in common use: ja , jc , and jc . it should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system air?w. ja this is the thermal resistance from junction to ambient (theta-ja, r-theta, etc.): (1) where t j is the junction temperature, t a , is the ambient air temperature, and q is the chip power. experimentally, ja is determined when a special thermal test die is assembled into the package of interest, and the part is mounted on the thermal test board. the diodes on the test chip are separately calibrated in an oven. the package/board is placed either in a jedec natural convection box or in the wind tunnel, the latter for forced con- vection measurements. a controlled amount of power (q) is dissipated in the test chip s heater resistor, the chip s temperature (t j ) is determined by the forward drop on the diodes, and the ambient temperature (t a ) is noted. note that ja is expressed in units of ?/w. jc this jedec designated parameter correlates the junction temperature to the case temperature. it is generally used to infer the junction temperature while the device is operating in the system. it is not considered a true thermal resistance and it is de?ed by: (2) u21 v dd 15 v dd 15 u22 v dd 15 v dd 15 v13 v dd 15 v dd 15 v14 v dd 15 v dd 15 v15 v dd 15 v dd 15 v20 v dd 15 v dd 15 v21 v dd 15 v dd 15 v22 v dd 15 v dd 15 w13 v dd 15 v dd 15 w14 v dd 15 v dd 15 w15 v dd 15 v dd 15 w20 v dd 15 v dd 15 w21 v dd 15 v dd 15 w22 v dd 15 v dd 15 y16 v dd 15 v dd 15 y17 v dd 15 v dd 15 y18 v dd 15 v dd 15 y19 v dd 15 v dd 15 t32 nc nc w32 nc nc table 45. ort82g5 680-pin pbgam (fpbga) pinout (continued) 680-pbgam v dd io bank vref group i/o pin description additional function 680-pbgam ja = t j ?t a q = t j ?t c q lattice semiconductor orca ORT42G5 and ort82g5 data sheet 115 where t c is the case temperature at top dead center, t j is the junction temperature, and q is the chip power. dur- ing the ja measurements described above, besides the other parameters measured, an additional temperature reading, t c , is made with a thermocouple attached at top-dead-center of the case. jc is also expressed in units of ?/w. jc this is the thermal resistance from junction to case. it is most often used when attaching a heat sink to the top of the package. it is de?ed by: (3) the parameters in this equation have been de?ed above. however, the measurements are performed with the case of the part pressed against a water-cooled heat sink to draw most of the heat generated by the chip out the top of the package. it is this difference in the measurement process that differentiates jc from jc . jc is a true thermal resistance and is expressed in units of ?/w. jb this is the thermal resistance from junction to board. it is de?ed by: (4) where t b is the temperature of the board adjacent to a lead measured with a thermocouple. the other parameters on the right-hand side have been de?ed above. this is considered a true thermal resistance, and the measure- ment is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. note that jb is expressed in units of ?/w and that this parameter and the way it is measured are still being dis- cussed by the jedec committee. fpsc maximum junction temperature once the power dissipated by the fpsc has been determined, the maximum junction temperature of the fpsc can be found. this is needed to determine if speed derating of the device from the 85 ? junction temperature used in all of the delay tables is needed. using the maximum ambient temperature, t amax , and the power dissipated by the device, q (expressed in ?), the maximum junction temperature is approximated by: (5) package thermal characteristics the thermal characteristics of the 484-ball pbgam (fpbga with heat spreader) used for the ORT42G5, the 680- ball pbgam (fpbga with heat spreader) and the 680-ball fpbga used for the ort82g5 are available in the ther- mal management section of the lattice web site at www .latticesemi.com . heat sink vendors for bga packages the estimated worst-case power requirements for the ORT42G5 and ort82g5 are in the 3 w to 5 w range. con- sequently, for most applications an external heat sink will be required. table 46 lists, in alphabetical order, heat sink vendors who advertise heat sinks aimed at the bga market. jc = t j ?t c q jb = t j ?t b q t jmax = t amax + (q ? jb ) lattice semiconductor orca ORT42G5 and ort82g5 data sheet 116 table 46. heat sink vendors package parasitics the electrical performance of an ic package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. table 47 lists eight parasitics associated with the orca packages. these parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. four inductances in nh are listed: l sw and l sl, the self-inductance of the lead; and l mw and l ml , the mutual inductance to the nearest neighbor lead. these parameters are important in determining ground bounce noise and inductive crosstalk noise. three capacitances in pf are listed: c m , the mutual capacitance of the lead to the near- est neighbor lead; and c 1 and c 2 , the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). these parameters are important in determining capacitive crosstalk and the capacitive loading effect of the lead. resistance values are in m . the parasitic values in table 47 are for the circuit model of bond wire and package lead parasitics. if the mutual capacitance value is not used in the designer s model, then the value listed as mutual capacitance should be added to each of the c 1 and c 2 capacitors. table 47. orca typical package parasitics figure 41. package parasitics package outline drawings package outline drawings for the 484-ball pbgam (fpbga) used for the ORT42G5 and 680-ball pbgam (fpbga) used for the ort82g5 are available in the package diagrams section of the lattice semiconductor web site at www .latticesemi.com . vendor location phone aavid thermalloy concord, nh (603) 224-9988 chip coolers warwick, ri (800) 227-0254 ierc burbank, ca (818) 842-7277 r-theta buffalo, ny (800) 388-5428 sanyo denki torrance, ca (310) 783-5400 wake?ld thermal solutions pelham, nh (800) 325-1426 l sw l mw r w c 1 c 2 c m l sl l ml 3.8 1.3 250 1.0 1.0 0.3 2.8-5 0.5 -1 pad n board pads c m c 1 l sw r w l sl l mw c 2 c 1 l ml c 2 pad n + 1 l sw r w l sl circuit pad n+1 pad n package pads lattice semiconductor orca ORT42G5 and ort82g5 data sheet 117 part number description device type options ordering information conventional packaging commercial 1 device voltage ORT42G5 1.5v internal 3.3/2.5/1.8/ 1.5v i/o ort82g5 1.5v internal 3.3/2.5/1.8/ 1.5v i/o device family part number speed grade package type ball count grade ORT42G5 ORT42G5-3bm484c 3 pbgam 484 c ORT42G5-2bm484c 2 pbgam 484 c ORT42G5-1bm484c 1 pbgam 484 c ort82g5 ort82g5-3f680c 3 pbgam (no heat spreader) 680 c ort82g5-2f680c 2 pbgam (no heat spreader) 680 c ort82g5-1f680c 1 pbgam (no heat spreader) 680 c ort82g5-3bm680c2 2 3 pbgam (with heat spreader) 680 c ort82g5-2bm680c 2 2 pbgam (with heat spreader) 680 c ort82g5-1bm680c 2 1 pbgam (with heat spreader) 680 c 1. for all but the slowest commercial speed grade, the speed grades on these devices are dual marked. for example, the commercia l speed grade -2xxxxxc is also marked with the industrial grade -1xxxxxi. the commercial grade is always one speed grade faster than th e associated dual mark industrial grade. the slowest commercial speed grade is marked as commercial grade only. 2. bm680 package was converted to f680 via pcn#09a-08. device family ORT42G5 = 4 serdes channels ort82g5 = 8 serdes channels ortx2g5 x x xx xxx xxx speed grade grade c = commercial i = industrial optional suffix blank = production es = engineering samples ball count 484 680 package bm = fine-pitch plastic ball grid array bmn = lead-free fine-pitch plastic ball grid array f = fine-pitch plastic ball grid array fn = lead-free fine-pitch plastic ball grid array lattice semiconductor orca ORT42G5 and ort82g5 data sheet 118 industrial 1 lead-free packaging commercial 1 industrial 1 device family part number speed grade package type ball count grade ORT42G5 ORT42G5-2bm484i 2 pbgam 484 i ORT42G5-1bm484i 1 pbgam 484 i ort82g5 ort82g5-2f680i 2 pbgam (no heat spreader) 680 i ort82g5-1f680i 1 pbgam (no heat spreader) 680 i ort82g5-2bm680i 2 2 pbgam (with heat spreader) 680 i ort82g5-1bm680i 2 1 pbgam (with heat spreader) 680 i 1. for all but the slowest commercial speed grade, the speed grades on these devices are dual marked. for example, the commercia l speed grade -2xxxxxc is also marked with the industrial grade -1xxxxxi. the commercial grade is always one speed grade faster than th e associated dual mark industrial grade. the slowest commercial speed grade is marked as commercial grade only. 2. bm680 package was converted to f680 via pcn#09a-08. device family part number speed grade package type ball count grade ORT42G5 ORT42G5-3bmn484c 3 lead-free pbgam 484 c ORT42G5-2bmn484c 2 lead-free pbgam 484 c ORT42G5-1bmn484c 1 lead-free pbgam 484 c ort82g5 ort82g5-3fn680c 3 lead-free fpga (no heat spreader) 2 680 c ort82g5-2fn680c 2 lead-free fpga (no heat spreader) 2 680 c ort82g5-1fn680c 1 lead-free fpga (no heat spreader) 2 680 c 1. for all but the slowest commercial speed grade, the speed grades on these devices are dual marked. for example, the commerci al speed grade -2xxxxxc is also marked with the industrial grade -1xxxxxi. the commercial grade is always one speed grade faster. 2. refer to the thermal management document at www .latticesemi.com for ja and jc information. device family part number speed grade package type ball count grade ORT42G5 ORT42G5-2bmn484i 2 lead-free pbgam 484 i ORT42G5-1bmn484i 1 lead-free pbgam 484 i ort82g5 ort82g5-2fn680i 2 lead-free fpga (no heat spreader) 2 680 i ort82g5-1fn680i 1 lead-free fpga (no heat spreader) 2 680 i 1. for all but the slowest commercial speed grade, the speed grades on these devices are dual marked. for example, the commerci al speed grade -2xxxxxc is also marked with the industrial grade -1xxxxxi. the commercial grade is always one speed grade faster. 2. refer to the thermal management document at www .latticesemi.com for ja and jc information. lattice semiconductor orca ORT42G5 and ort82g5 data sheet 119 technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www .latticesemi.com revision history date version change summary previous lattice releases. july 2008 07.0 bm680 conversion to f680 per pcn#09a-08. |
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